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FFP08H60S 데이터시트(PDF) 10 Page - Fairchild Semiconductor

부품명 FFP08H60S
상세설명  PFCPWM Combination Controller
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제조업체  FAIRCHILD [Fairchild Semiconductor]
홈페이지  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

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AN-8027
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.0 • 8/26/09
10
40dB
20dB
0dB
-20dB
-40dB
10Hz
100Hz
1kHz
10kHz 100kHz
f
IZ
Control-to-output
1MHz
f
IC
Compensation
Closed Loop Gain
60dB
f
IP
Figure 17. Current Loop Compensation
(Design Example)
Setting the crossover frequency
as 7kHz:
11
@
36
2
0.1 387
0.66
2.55 2
7 10 524 10
IC
CS
CS
BOUT
IEA
RAMP
IC
BOOST
ff
vR
V
vV
f
L
π
π
=
=
⋅⋅
==
⋅⋅ ×
×
)
)
6
1
@
11
17
88 10
0.66
IC
IC
CS
MI
IEA
ff
R
k
v
G
v
=
==
=
Ω
×⋅
)
)
1
33
11
4
2/ 3
17 10 2
7 10 / 3
IC
IC
C
CnF
Rf
π
π
==
=
×⋅
⋅ ×
Setting the pole of the compensator at 70kHz,
2
33
11
0.13
2
270 10 17 10
IC
IP
IC
CnF
fR
π
π
==
=
⋅⋅
⋅×
⋅ ×
[STEP-9] PFC Voltage Loop Design
Since FAN480X employs line feed-forward, the power
stage transfer function becomes independent of the line
voltage. Then, the low-frequency, small-signal, control-to-
output transfer function is obtained as:
ˆ
1
ˆ
5
BOUT
BOUT
MAX
EA
BOUT
vI
K
vsC
≅⋅
(37)
where:
ˆ
1
ˆ
5
BOUT
BOUT
MAX
EA
BOUT
vI
K
vsC
≅⋅
(38)
Proportional and integration (PI) control with high-
frequency pole is typically used for compensation. The
compensation zero (fVZ) introduces phase boost, while the
high-frequency compensation pole (fVP) attenuates the
switching ripple, as shown in Figure 18.
Figure 18. Voltage Loop Compensation
The transfer function of the compensation network is
obtained as:
1
ˆ
22
ˆ
1
2
COMP
VI
VZ
OUT
VP
s
vf
f
s
vs
f
ππ
π
+
=⋅
+
(39)
where:
11
2
2.5
1
,
22
1
2
MV
VI
VZ
BOUT
VC
VC
VC
VP
VC
VC
G
f
f
and
VC
R
C
f
RC
ππ
π
=⋅
=
⋅⋅
=
⋅⋅
(40)
The procedure to design the feedback loop is as follows:
(a) Determine the crossover frequency (fVC) around
1/10~1/5 of the line frequency. Since the control-to-
output transfer function of power stage has -20dB/dec
slope and -90o phase at the crossover frequency, as
shown in Figure 18 as 0dB; it is necessary to place the
zero of the compensation network (fVZ) around the
crossover frequency so that 45
° phase margin is
obtained. Then, the capacitor CVC1 is determined as:
1
2
2.5
5(2
)
MV
BOUT
MAX
VC
BOUT
BOUT
VC
GI
K
C
V
Cf
π
⋅⋅
=⋅
⋅⋅
(41)
To place the compensation zero at the crossover
frequency, the compensation resistor is obtained as:
1
1
2
VC
VC
VC
R
fC
π
=
⋅⋅
(42)
(b)
Place compensator high-frequency pole (fVP) at least
a decade higher than fC to ensure that it does not
interfere with the phase margin of the voltage
regulation loop at its crossover frequency. It should
also be sufficiently lower than the switching
frequency of the converter so noise can be effectively
attenuated. Then, the capacitor CVC2 is determined as:
2
1
2
VC
VP
VC
C
fR
π
=
⋅⋅
(43)


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