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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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FAN5236MTCX 데이터시트(PDF) 11 Page - Fairchild Semiconductor |
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FAN5236MTCX 데이터시트(HTML) 11 Page - Fairchild Semiconductor |
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11 / 19 page  © 2002 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5236 • Rev. 1.3.2 11 Initialization and Soft Start Assuming EN is HIGH, FAN5236 is initialized when VCC exceeds the rising UVLO threshold. Should VCC drop below the UVLO threshold, an internal power-on reset function disables the chip. The voltage at the positive input of the error amplifier is limited by the voltage at the SS pin, which is charged with a 5 μA current source. Once CSS has charged to VREF (0.9V) the output voltage is in regulation. The time it takes SS to reach 0.9V is: 5 xC 9 . 0 t SS 9 . 0 = (1) where t0.9 is in seconds if CSS is in μF. When SS reaches 1.5V, the power-good outputs are enabled and Hysteretic Mode is allowed. The converter is forced into PWM Mode during soft-start. Operation Mode Control The mode-control circuit changes the converter mode from PWM to hysteretic and vice versa, based on the voltage polarity of the SW node when the lower MOSFET is conducting and just before the upper MOSFET turns on. For continuous inductor current, the SW node is negative when the lower MOSFET is conducting and the converters operate in fixed- frequency PWM Mode, as shown in Figure 11. This mode achieves high efficiency at nominal load. When the load current decreases to the point where the inductor current flows through the lower MOSFET in the ‘reverse’ direction, the SW node becomes positive and the mode is changed to hysteretic, which achieves higher efficiency at low currents by decreasing the effective switching frequency. To prevent accidental mode change or "mode chatter," the transition from PWM to Hysteretic Mode occurs when the SW node is positive for eight consecutive clock cycles, as shown in Figure 11. The polarity of the SW node is sampled at the end of the lower MOSFET conduction time. At the transition between PWM and Hysteretic Mode, the upper and lower MOSFETs are turned off. The phase node “rings” based on the output inductor and the parasitic capacitance on the phase node and settles out at the value of the output voltage. The boundary value of inductor current, where current becomes discontinuous, can be estimated by the following expression: ⎟⎟ ⎟ ⎠ ⎞ ⎜⎜ ⎜ ⎝ ⎛ − = IN OUT SW OUT OUT IN ) DIS ( LOAD V L F 2 V ) V V ( I (2) PWMMode HystereticMode HystereticMode PWMMode 1 234 567 8 VCORE I L 0 VCORE I L 0 1 23 4 5 6 7 8 Figure 11. Transitioning Between PWM and Hysteretic Mode Hysteretic Mode Conversely, the transition from Hysteretic Mode to PWM Mode occurs when the SW node is negative for eight consecutive cycles. A sudden increase in the output current causes a change from Hysteretic to PWM Mode. This load increase causes an instantaneous decrease in the output voltage due to the voltage drop on the output capacitor ESR. If the load causes the output voltage (as presented at VSNS) to drop below the hysteretic regulation level (20mV below VREF), the mode is changed to PWM on the next clock cycle. In Hysteretic Mode, the PWM comparator and the error amplifier that provide control in PWM Mode are inhibited and the hysteretic comparator is activated. In Hysteretic Mode, the low-side MOSFET is operated as a synchronous rectifier, where the voltage across VDS(ON) is monitored and switched off when VDS(ON) goes positive (current flowing back from the load), allowing the diode to block reverse conduction. The hysteretic comparator initiates a PFM signal to turn on HDRV at the rising edge of the next oscillator clock, when the output voltage (at VSNS) falls below the lower threshold (10mV below VREF) and terminates the PFM signal or when VSNS rises over the higher threshold (5mV above VREF). The switching frequency is primarily a function of: Spread between the two hysteretic thresholds ILOAD Output inductor and capacitor ESR. |
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