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FAN6204MY 데이터시트(PDF) 11 Page - Fairchild Semiconductor |
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FAN6204MY 데이터시트(HTML) 11 Page - Fairchild Semiconductor |
11 / 14 page © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6204 • Rev. 1.0.0 11 IM SR Gate 4.8µs 4.8µs 4.8µs 3 Times Green Mode Normal Mode Figure 20. Entering Green Mode Figure 21. Resuming Normal Operation Causal Function Causal function is utilized to limit the time interval (tSR- MAX) from the rising edge of VLPC to the falling edge of the SR gate. tSR-MAX is limited to 97% of previous switching period, as shown in Figure 22. When the system operates at fixed frequency, whether voltage- second balance theorem can be applied or not, causal function can guarantee reliable operation. Figure 22. Causal Function Operation Fault Causal Timing Protection Fault causal timing protection is utilized to disable the SR gate under some abnormal conditions. Once the switching period (tS-PWM(n)) is longer than 120% of previous switching period (tS-PWM(n-1)), SR gate is disabled and enters Green Mode, as shown in Figure 23. Since the rising edge of VLPC among switching periods (tS-PWM) is tracked for causal function, the accuracy of switching period is important. Therefore, if the detected switching period has a serious variation under some abnormal conditions, the SR gate should be terminated to prevent fault trigger. Figure 23. Fault Causal Timing Protection Gate Expand Limit Protection Gate expand limit protection controls on-time expansion of the SR MOSFET. Once the discharge time of the internal timing capacitor (tDIS.CT) is longer than 115% of previous on time of the SR MOSFET (ton-SR(n-1)); ton-SR(n) is limited to 115% of ton-SR(n-1), as shown in Figure 24. When output load changes rapidly from light load to heavy load, voltage-second balance theorem may not be applied. In this transient state, gate expand limit protection is activated to prevent overlap between SR gate and PWM gate. Figure 24. Gate Expand Limit Protection RES Dropping Protection RES dropping protection prevents VRES dropping too much within a cycle. The VRES is sampled as a reference voltage, VRES’, on VLPC rising edge. Once VRES drops below 90% of VRES’ for longer than a debounce time (tRES-DROP), the SR gate is turned off immediately, as shown in Figure 25. When output voltage drops rapidly within a switching cycle, voltage-second balance may not be applied, RES dropping protection is activated to prevent overlap. Figure 25. VRES Dropping Protection |
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