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FAN3225T 데이터시트(PDF) 6 Page - Fairchild Semiconductor

부품명 FAN3225T
상세설명  30V PMOS-NMOS Bridge Driver
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제조업체  FAIRCHILD [Fairchild Semiconductor]
홈페이지  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

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© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN3278 • Rev. 1.0.0
6
Electrical Characteristics
Unless otherwise noted, VDD=12V and TJ=-40°C to +125°C. Currents are defined as positive into the device (Isink) and
negative out of the device (Isource).
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Supply
VDD
Optimum Operating Range
(8)
8
27
V
IDD
Supply Current Inputs / EN Not
Connected
1.3
2.0
mA
VON
Turn-On Voltage
(9)
INA=ENA=VDD, INB=ENB=0V
3.8
V
VHYS
Turn-On / Turn-Off Hysteresis
(9)
INA=ENA=VDD, INB=ENB=0V
10
mV
Input
(9)
VIL
INx Logic Low Threshold
0.8
1.1
V
VIH
INx Logic High Threshold
1.80
2.25
V
VHYS
Logic Hysteresis Voltage
0.4
0.7
1.0
V
Enable
VENL
Enable Logic Low Threshold
EN from 5V to 0V
0.8
1.2
V
VENH
Enable Logic High Threshold
EN from 0V to 5V
1.60
2.25
V
VHYS
Logic Hysteresis Voltage
(10)
0.7
V
RPU
Enable Pull-Up Resistance
100
kΩ
tD1
Propagation A Delay, EN Rising
(11)
0 - 5VIN, 1V/ns Slew Rate
44
70
ns
tD2
Propagation A Delay, EN Falling
(11)
0 – 5VIN, 1V/ns Slew Rate
33
60
ns
tD2
Propagation B Delay, EN Rising
(11)
0 - 5VIN, 1V/ns Slew Rate
39
70
ns
tD1
Propagation B Delay, EN Falling
(11)
0 – 5VIN, 1V/ns Slew Rate
29
60
ns
Continued on the following page…
Timing Diagrams
Figure 5. Non-Inverting
Figure 6. Inverting
90%
10%
Output
Input
or
Enable
t
D1
t
D2
t
RISE
t
FALL
V
INL
V
INH


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