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FAN7530 데이터시트(PDF) 13 Page - Fairchild Semiconductor |
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FAN7530 데이터시트(HTML) 13 Page - Fairchild Semiconductor |
13 / 37 page © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN9611 / FAN9612 • Rev. 1.1.3 13 4. Analog Ground (AGND) and Power Ground (PGND) Analog ground connection (AGND) is the GND for all control logic biased from the 5V rail. Internally, the AGND and PGND pins are tied together by two anti- parallel diodes to limit ground bounce difference due to bond wire inductances during the switching actions of the high-current gate drive circuits. It is recommended to connect AGND and PGND pins together with a short, low-impedance trace on the PCB (right under the IC). PGND is the reference potential (0V) for the high- current gate-drive circuit. Two bypass capacitors should be connected between the VDD pin and the PGND pin. One is the VDD energy storage capacitor, which provides bias power during startup until the bootstrap power supply comes up. The other capacitor shall be a good- quality ceramic bypass capacitor, as close as possible to PGND and VDD pins to filter the high peak currents of the gate driver circuits. The value of the ceramic bypass capacitor is a strong function of the gate charge requirement of the power MOSFETs and its recommended value is between 1µF and 4.7µF to ensure proper operation. 5. Soft-Start (SS) Soft-start is programmed with a capacitor between the SS pin and AGND. This is the non-inverting input of the transconductance (gM) error amplifier. At startup, the soft-start capacitor is quickly pre-charged to a voltage approximately 0.5V below the voltage on the feedback pin (FB) to minimize startup delay. Then a 5µA current source takes over and charges the soft-start capacitor slowly, ramping up the voltage reference of the error amplifier. By ramping up the reference slowly, the voltage regulation loop can stay closed, actively controlling the output voltage during startup. While the SS capacitor is charging, the output of the error amplifier is monitored. In case the error voltage (COMP) ever exceeds 3.5V, indicating that the voltage loop is close to saturation, the 5µA soft-start current is reduced. Therefore, the soft start is automatically extended to reduce the current needed to charge the output capacitor, reducing the output power during startup. This mechanism is integrated to prevent the voltage loop from saturation. The charge current of the soft-start capacitor can be reduced from the initial 5µA to as low as 0.5µA minimum. In addition to modulating the soft-start current into the SS capacitor, the SS pin is clamped 0.2V above the FB pin. This is useful in preventing the SS capacitor from running away from the FB pin and defeating the closed- loop soft-start. During the zero crossing of the input source waveform, the input power is almost zero and the output voltage can not be raised. Therefore the FB voltage stays flat or even decays while the SS voltage keeps rising. This is a problem if closed-loop soft-start should be maintained. By clamping the SS voltage to the FB pin, this problem can be mitigated. Furthermore, during brownout condition, the output voltage of the converter might fall, which is reflected at the FB pin. When FB voltage goes 0.5V below the voltage on the SS pin, it starts discharging the soft-start capacitor. The soft-start capacitor remains 0.5V above the FB voltage. When the brownout condition is over, the converter returns to normal operation gracefully, following the slow ramp up of the soft-start capacitor at the non-inverting input of the error amplifier. Figure 19. Soft-Start Programming 6. Error Amplifier Compensation (COMP) COMP pin is the output of the error amplifier. The voltage loop is compensated by a combination of RS and CS to AGND at this pin. The control range of the error amplifier is between 0.195V and 4.3V. When the COMP voltage is below about 0.195V, the PWM circuit skips pulses. Above 4.3V, the maximum on-time limit terminates the conduction of the boost switches. Due to the input-voltage feedforward, the output of the error amplifier is proportional to the input power of the converter, independent of the input voltage. In addition, also due to the input-voltage feedforward, the maximum power capability of the converter and the loop gain is independent of the input voltage. The controller’s phase- management circuit monitors the error amplifier output and switches to single-phase operation when the COMP voltage falls below 0.73V and returns to two-phase operation when the error voltage exceeds 0.93V. These thresholds correspond to about 13% and 18% of the maximum power capability of the design. |
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