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FAN7530 데이터시트(PDF) 18 Page - Fairchild Semiconductor |
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FAN7530 데이터시트(HTML) 18 Page - Fairchild Semiconductor |
18 / 37 page © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN9611 / FAN9612 • Rev. 1.1.3 18 Application Information 1. Synchronization and Timing Functions The FAN9611/12 employs a sophisticated synchronization sub-system. At the heart of the system is a dual-channel switching-frequency detector that measures the switching period of each channel in every switching cycle and locks their operating phase 180 degrees out of phase from each other. The slower operating frequency channel is dominant, but there is no master-slave arrangement. Moreover, as the frequency constantly changes due to the varying input voltage, either channel can be the slower dominant channel. As opposed to the most common technique, where the phase relationship between the channels is provided by changing the on-time of one of the MOSFETs, the FAN9611/12 controls the phase relationship by inserting a turn-on delay before the next switching period starts for the faster running phase. As shown in the literature [1], the on-time modulation technique is not stable under all operating conditions, while the off-time modulation (or delaying the turn-on) is unconditionally stable under all operating conditions. a. Restart Timer and Dead-Phase Detect Protection The restart timer is an integral part of the Sync-Lock™ synchronizing circuit. It ensures exact 180-degree out- of-phase operation in restart timer operation. This is an important safety feature. In the case of a non-operating phase due to no ZCD detection, missing gate drive connection (for example no gate resistor), one of the power components failing in an open circuit, or similar errors, the other phase is locked into restart timer operation, preventing it from trying to deliver full power to the load. This is called the dead-phase detect protection. The restart timer is set to approximately 16.5kHz, just above the audible frequency range, to avoid any acoustic noise generation. b. Frequency Clamp Just as the restart timer, the frequency clamp is integrated into the synchronization and ensures exact 180-degree out-of-phase operation when the operating frequency is limited. This might occur at very light-load operation or near the zero crossing region of the line voltage waveform. Limiting the switching frequency at light load can improve efficiency, but has a negative effect on power factor since the converter also enters true DCM operation. The frequency clamp is set to approximately 525kHz. 2. FAN9612 Startup with 12V Bias (Less than UVLO) The FAN9612 (not FAN9611) is designed so that the controller can start even if the auxiliary bias voltage is less than the controller’s under-voltage lockout start threshold. This is useful if the auxiliary power is 12V or below. This configuration also allows bias power designs using a bootstrap winding to start the FAN9612 without a dedicated startup resistor. In the boost PFC topology, the output voltage is pre- charged to the peak line voltage by the boost diode. As soon as voltage is present at the output of the boost converter, current starts to flow through the feedback resistors from the boost output to GND. Using an external low-voltage MOSFET in series with the lower resistor in the feedback divider, as shown in Figure 27; this current can be diverted to charge the VDD bypass capacitor of the controller. The upper resistor becomes a current source to charge the capacitor. To accomplish this, a small external diode should be connected between the VDD and FB pins. As VDD rises past the under-voltage lockout threshold of the IC, the 5V reference is turned on, which turns on the external MOSFET and connects the resistor of the feedback divider to ground. The IC checks if the FB voltage is below 3.22V, ensuring that the FB pin is in its normal operating voltage range, before enabling the rest of the IC operation. The diode between the FB pin and the VDD pin is reverse biased and the FB pin reverts to its normal role of output voltage sensing. A simplified circuit implementation for this proprietary startup method is shown in Figure 27. If, for whatever reason, the bias to the IC drops below the under-voltage lockout level, the startup process is repeated. Figure 27. Simplified FAN9612 Startup Circuit Using the Output Feedback Resistors to Provide a Charging Current |
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