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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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DAC7563SDSCR 데이터시트(PDF) 7 Page - Texas Instruments |
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DAC7563SDSCR 데이터시트(HTML) 7 Page - Texas Instruments |
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7 / 56 page  SCLK SYNC DIN VOUT DB23 DB0 LDAC (1) LDAC (2) CLR t 2 t 7 t 6 t 9 t 10 t 8 t 4 t 5 t 3 t 1 t 12 t 13 t 14 t 11 DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563 www.ti.com SLAS719C – AUGUST 2010 – REVISED JUNE 2011 TIMING DIAGRAM (1) Asynchronous LDAC update mode. For more information, see the LDAC Functionality section. (2) Synchronous LDAC update mode; LDAC remains low. For more information, see the LDAC Functionality section. Figure 1. Serial Write Operation TIMING REQUIREMENTS (1) (2) At AVDD = 2.7 V to 5.5 V and over –40°C to 125°C (unless otherwise noted). DAC756x/DAC816x/DAC856x PARAMETER UNIT MIN TYP MAX t1 SCLK falling edge to SYNC falling edge (for successful write operation) 10 ns t2 (3) SCLK cycle time 20 ns t3 SYNC rising edge to 23rd SCLK falling edge (for successful SYNC interrupt) 13 ns t4 Minimum SYNC HIGH time 80 ns t5 SYNC to SCLK falling edge setup time 13 ns t6 SCLK LOW time 8 ns t7 SCLK HIGH time 8 ns t8 SCLK falling edge to SYNC rising edge 10 ns t9 Data setup time 6 ns t10 Data hold time 5 ns t11 SCLK falling edge to LDAC falling edge for asynchronous LDAC update mode 5 ns t12 LDAC pulse duration, LOW time 10 ns t13 CLR pulse duration, LOW time 80 ns t14 CLR falling edge to start of VOUT transition 100 ns (1) All input signals are specified with tR = tF = 3 ns (10% to 90% of AVDD) and timed from a voltage level of (VINL + VINH)/2. (2) See the Serial Write Operation timing diagram (Figure 1). (3) Maximum SCLK frequency is 50 MHz at AVDD = 2.7 V to 5.5 V. Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563 |
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