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STK14C88 데이터시트(PDF) 6 Page - Cypress Semiconductor

부품명 STK14C88
상세설명  32 K x 8 AutoStore nvSRAM Commercial, industrial, military temperatures
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제조업체  CYPRESS [Cypress Semiconductor]
홈페이지  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

STK14C88 데이터시트(HTML) 6 Page - Cypress Semiconductor

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STK14C88
Document Number: 001-52038 Rev. *C
Page 6 of 20
Figure 5. SRAM Read Cycle 2: E and G Controlled [6]
SRAM Read Cycles #1 and #2
(VCC = 5.0 V ± 10%)[4]
NO.
Symbols
Parameter
STK14C88-25 STK14C88-35 STK14C88-45
Unit
Min
Max
Min
Max
Min
Max
#1, #2
Alt.
1tELQV
tACS
Chip Enable Access Time
25
35
45
ns
2tAVAV
[6]
, tELEH
[6]
tRC
Read Cycle Time
25
35
45
ns
3tAVQV
7
tAA
Address Access Time
25
35
45
ns
4tGLQV
tOE
Output Enable to Data Valid
10
15
20
ns
5tAXQX
[7]
tOH
Output Hold after Address Change
5
5
5
ns
6tELQX
tLZ
Address Change or Chip Enable to
Output Active
5–
5
5
ns
7tEHQZ
[8]
tHZ
Address Change or Chip Disable to
Output Inactive
–10
13
15
ns
8tGLQX
tOLZ
Output Enable to Output Active
0
0
0
ns
9tGHQZ
[8]
tOHZ
Output Disable to Output Inactive
10
13
15
ns
10
tELICCH
[5]
tPA
Chip Enable to Power Active
0
0
0
ns
11
tEHICCL
[5]
tPS
Chip Disable to Power Standby
25
35
45
ns
Figure 4. SRAM Read Cycle 1: Address Controlled [6, 7]
Notes
6. W and HSB must be high during SRAM read cycles.
7. I/O state assumes E and G
< V
IL and W  VIH; device is continuously selected.
8. Measured ± 200 mV from steady state output voltage.
DATA VALID
5
tAXQX
3
tAVQV
DQ (DATA OUT)
ADDRESS
2
tAVAV
2
29
11
7
9
10
8
4
3
6
1
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