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STK15C88-NF45TR 데이터시트(PDF) 10 Page - Cypress Semiconductor

부품명 STK15C88-NF45TR
상세설명  256-Kbit (32 K x 8) PowerStore nvSRAM Unlimited RECALL Cycles
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제조업체  CYPRESS [Cypress Semiconductor]
홈페이지  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

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STK15C88
Document Number: 001-50593 Rev. *C
Page 10 of 17
SRAM Write Cycle
Parameter
Description
25 ns
45 ns
Unit
Min
Max
Min
Max
Cypress
Parameter
Alt
tWC
tAVAV
Write Cycle Time
25
45
ns
tPWE
tWLWH, tWLEH
Write Pulse Width
20
30
ns
tSCE
tELWH, tELEH
Chip Enable To End of Write
20
30
ns
tSD
tDVWH, tDVEH
Data Setup to End of Write
10
15
ns
tHD
tWHDX, tEHDX
Data Hold After End of Write
0
0
ns
tAW
tAVWH, tAVEH
Address Setup to End of Write
20
30
ns
tSA
tAVWL, tAVEL
Address Setup to Start of Write
0
0
ns
tHA
tWHAX, tEHAX
Address Hold After End of Write
0
0
ns
tHZWE
[7,8]
tWLQZ
Write Enable to Output Disable
10
15
ns
tLZWE
[7]
tWHQX
Output Active After End of Write
5
5
ns
Switching Waveforms
Figure 7. SRAM Write Cycle 1: WE Controlled [8]
Figure 8. SRAM Write Cycle 2: CE Controlled [8]
tWC
tSCE
tHA
tAW
tSA
tPWE
tSD
tHD
tHZWE
tLZWE
ADDRESS
CE
WE
DATA IN
DATA OUT
DATA VALID
HIGH IMPEDANCE
PREVIOUS DATA
tWC
ADDRESS
tSA
tSCE
tHA
tAW
tPWE
tSD
tHD
CE
WE
DATA IN
DATA OUT
HIGH IMPEDANCE
DATA VALID
Notes
8. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
9. CE or WE must be greater than VIH during address transitions.
[+] Feedback


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