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TMP320LC2401AVFS 데이터시트(PDF) 10 Page - Texas Instruments |
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TMP320LC2401AVFS 데이터시트(HTML) 10 Page - Texas Instruments |
10 / 88 page TMS320LF2401A, TMS320LC2401A DSP CONTROLLERS SPRS161K − MARCH 2001 − REVISED JULY 2007 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 terminal functions (continued) Terminal Functions† (Continued) TERMINAL DESCRIPTION NAME NO. DESCRIPTION ADCIN00 17 Analog input channel 0 ADCIN01 16 Analog input channel 1 ADCIN02 15 Analog input channel 2 ADCIN03 14 Analog input channel 3 ADCIN04 13 Analog input channel 4 VCCA 19 Analog supply voltage for ADC (3.3 V)‡ Internally connected to VREFHI VSSA 18 Analog ground reference for ADC. Internally connected to VREFLO . SCITXD/IOPB3 3 SCI asynchronous serial port transmit data or GPIO ( ↑) SCIRXD/IOPB4 2 SCI asynchronous serial port receive data or GPIO ( ↑) TCK/IOPB1 4 JTAG test clock or GPIO ( ↑) Function when TRST = 0: IOPB1 Function when TRST = 1: TCK TDI/OPB5§ 24 JTAG test data input or GPO. When TRST is low (i.e., when the JTAG connector is not connected to the DSP), the TDI/OPB5 pin acts as an output. When RS is low, the OPB5 pin is asynchronously forced into a high-impedance state and when RS subsequently rises, it will remain in high-impedance state until software configures this pin as an output. The B5DIR bit (bit 13 of the PBDATDIR register) controls the enable to this output buffer. Bit 13 of the MCRA register will have no effect on this pin. ( ↑) This pin must be held low during a reset to invoke the on-chip boot ROM. Function when TRST = 0: OPB5 Function when TRST = 1: TDI TDO/IOPB2 23 JTAG scan out, test data output or GPIO ( ↓) Function when TRST = 0: IOPB2 Function when TRST = 1: TDO TMS/XF 1 JTAG test mode select or GPO. External flag output (latched software-programmable signal). XF is a general-purpose output pin. It is set/reset by the SETC XF/CLRC XF instruction. This pin is configured as an external flag output by all device resets. ( ↑) Function when TRST = 0: XF Function when TRST = 1: TMS NOTE: The enabling/disabling of the XF pin is controlled by Bit 0 of the SCSR4 register at address 0x701B (in addition to the TRST pin). Upon reset, this bit is zero, disabling the XF pin. This bit must be set by user code before it can be used. This bit is not readable; hence, its status cannot be determined. † Bold face type indicates function of the device pin after reset. ‡ It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy and improve the noise immunity of the ADC. § TDI is MUXed with digital output, not digital I/O. ¶ Pin 26 is VCCP on LF2401A and is a No Connect (NC) on LC2401A. LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±20 µA.) NOTE: On the target hardware, pins 13 and 14 (EMU0/EMU1) of the JTAG header must be pulled high. |
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