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ISL22346WFV20Z 데이터시트(PDF) 1 Page - Intersil Corporation |
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ISL22346WFV20Z 데이터시트(HTML) 1 Page - Intersil Corporation |
1 / 16 page 1 ® FN6177.2 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006, 2008, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL22346 Quad Digitally Controlled Potentiometers (XDCP™) Low Noise, Low Power I2C™ Bus, 128 Taps The ISL22346 integrates four digitally controlled potentiometers (DCP) and non-volatile memory on a monolithic CMOS integrated circuit. The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the I2C bus interface. Each potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR) that can be directly written to and read by the user. The contents of the WR controls the position of the wiper. At power-up the device recalls the contents of the two DCP’s IVR to the corresponding WRs. The DCPs can be used as a three-terminal potentiometers or as a two-terminal variable resistors in a wide variety of applications including control, parameter adjustments, and signal processing. Features • Four potentiometers in one package • 128 resistor taps •I2C serial interface - Three address pins, up to eight devices/bus • Non-volatile storage of wiper position • Wiper resistance: 70 Ω typical @ V CC = 3.3V • Shutdown mode • Shutdown current 5µA max • Power supply: 2.7V to 5.5V •50k Ω or 10kΩ total resistance • High reliability - Endurance: 1,000,000 data changes per bit per register - Register data retention: 50 years @ T < +55°C • 20 Ld TSSOP or 20 Ld TQFN package • Pb-free (RoHS compliant) Pinouts ISL22346 (20 LD TSSOP) TOP VIEW ISL22346 (20 LD TQFN) TOP VIEW RW0 RL0 RH0 SHDN VCC A1 A0 RH1 RL1 RW1 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 RH3 RL3 RW3 A2 SCL SDA GND RW2 RL2 RH2 1 2 3 4 6 18 20 19 RL3 RH2 RW1 8 17 9 RH1 RW0 RL1 15 14 13 12 7 RL0 RH3 16 5 RW3 RL2 11 10 O Data Sheet September 3, 2009 |
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