전자부품 데이터시트 검색엔진 |
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ISL45042 데이터시트(PDF) 8 Page - Intersil Corporation |
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ISL45042 데이터시트(HTML) 8 Page - Intersil Corporation |
8 / 9 page 8 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6072.9 April 13, 2011 ISL45042 Truth Table The ISL45042 truth table is shown in Table 2. For proper operation the CE should be disabled (pulled low) before powering the device down to assure that the glitches and transients will not cause unwanted EEPROM overwriting. . TABLE 2. TRUTH TABLE INPUT OUTPUT CTL CE VDD OUT ICC MEMORY Mid to Hi Hi VDD Increment Normal X Mid to Lo Hi VDD Decrement Normal X X Lo VDD No Change Increased Read >4.9V Hi VDD No Change Increased Program CTL VDD/2 CTL LOW CTL HIGH CE 78 79 7A 7B 7A UNDEF. COUNTER OUTPUT CTLILMPW CTLMTC CTLIHRPW CTLILRPW FIGURE 8. ISL45042 TIMING DIAGRAM VCOM CEST IGNORES 1ST PULSE AFTER PROGRAMMING STOP PROGRAMMING AFTER POWER IS 1ST APPLIED, THE VERY 1ST CTL PULSE IS IGNORED THE TIMING DIAGRAM ABOVE SHOWS POST POWER-UP TIMING. NOTE: START PROGRAMMING START PROGRAMMING CTLIHMPW ISL45042 |
유사한 부품 번호 - ISL45042_11 |
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유사한 설명 - ISL45042_11 |
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