74LVC2G34

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Product data sheet

Rev. 5 — 2 September 2010

3 of 17

NXP Semiconductors

74LVC2G34

Dual buffer gate

6.

Pinning information

6.1 Pinning

6.2 Pin description

7.

Functional description

[1]

H = HIGH voltage level; L = LOW voltage level.

Fig 4.

Pin configuration SOT363

and SOT457

Fig 5.

Pin configuration SOT886

Fig 6.

Pin configuration SOT891,

SOT1115 and SOT1202

74LVC2G34

1A

1Y

GND

2A

2Y

001aab676

1

2

3

6

5

4

74LVC2G34

GND

001aab677

1A

2A

1Y

2Y

Transparent top view

2

3

1

5

4

6

74LVC2G34

GND

001aag030

1A

2A

1Y

2Y

Transparent top view

2

3

1

5

4

6

Table 3.

Pin description

Symbol

Pin

Description

1A

1

data input

GND

2

ground (0 V)

2A

3

data input

2Y

4

data output

5

supply voltage

1Y

6

data output

Table 4.

Function table[1]

Input

Output

nA

nY

LL

HH