GENNUM CORPORATION

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When the signal strength decreases to the level set at the

"Carrier Detect Threshold Adjust" pin, the SSI/CD voltage

goes to a logic "0" state (0.8 V) and can be used to drive

other TTL/CMOS compatible logic inputs. When loss of

carrier is detected, the SDO/SDO outputs are muted (set to

a known static state). Additional SSI/CD output source

current can be obtained in applications with a pull-up

resistor. An external 5k pull-up resistor with less than 50pF

capacitor loading is recommended.

1.2 Carrier Detect Threshold Adjust

Carrier Detect Threshold Adjust is designed for applications

such as routers where signal crosstalk and circuit noise

cause the equalizer to output erroneous data when no input

signal is present. The GS9025A solves this problem with a

user

adjustable

threshold

which

meets

the

unique

conditions that exist in each application. Override and

internal default settings are provided to give the user total

flexibility.

The threshold level at which loss of carrier is detected is

adjustable via external resistors at the CD_ADJ pin. The

control voltage at the CD_ADJ pin is set by a simple resistor

divider

circuit

(see

Typical

Application

Circuit).

The

threshold level is adjustable from 200m to 350m. By default

(no external resistors), the threshold is typically 320m. In

noisy environments, it is not recommended to leave this pin

muting function and allows for maximum possible cable

length equalization.

1.3 Output Eye Monitor Test

The GS9025A provides an 'Output Eye Monitor Test'

(OEM_TEST) which allows the verification of signal integrity

after equalization, prior to reslicing. The OEM_TEST pin is

an open collector current output that requires an external

50

Ω pull-up resistor. When the pull-up resistor is not used,

the

OEM_TEST

block

is

disabled

and

the

internal

OEM_TEST circuit is powered down. The OEM_TEST

oscilloscope input. Due to additional power consumed by

this diagnostic circuit, it is not recommended for continuous

operation.

NOTE:

For

maximum

cable

length

performance

the

OEM_TEST block should be disabled.

2. RECLOCKER

The reclocker receives a differential serial data stream from

the internal multiplexer. It locks an internal clock to the

incoming data. It outputs the differential PECL retimed data

signal on SDO/SDO. It outputs the recovered clock on

SCO/SCO. The timing between the output and clock signals

is shown in Figure 17.

Fig. 17 Output and Clock Signal Timing

The reclocker contains four main functional blocks: the

Phase Locked Loop, Frequency Acquisition, Logic Circuit,

and Auto/Manual Data Rate Select.

2.1 Phase Locked Loop (PLL)

The Phase Locked Loop locks the internal PLL clock to the

incoming data rate. A simplified block diagram of the PLL is

shown below. The main components are the VCO, the

Phase Detector, the Charge Pump, and the Loop Filter.

Fig. 18 Simplified Block Diagram of the PLL

2.1.1 VCO

The VCO is a differential low phase noise, factory trimmed

design that provides increased immunity to PCB noise and

precise control of the VCO centre frequency. The VCO

operates between 30 and 540Mb/s and has a pull range of

±15% about the centre frequency. A single low impedance

noise and reduces the PLL's sensitivity to PCB noise.

frequencies. When SMPTE = SS0 = logic 1, the VCO centre

SMPTE/SS0 combinations, the VCO centre frequency

SDO

SCO

50%

DDI/DDI

LF+

LFS

LF-

VCO

DIVISION

2

PHASE

DETECTOR

INTERNAL

PLL CLOCK

CHARGE

PUMP

LOOP

FILTER