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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TS1100 데이터시트(PDF) 8 Page - Touchstone Semiconductor Inc |
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TS1100 데이터시트(HTML) 8 Page - Touchstone Semiconductor Inc |
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8 / 11 page  TS1100 Page 8 TS1100DS r1p0 RTFDS or S LOA x RSENSE RGA N Since the FET’s drain terminal is connected to R OUT, the output voltage of the TS1100 at the OUT terminal is, therefore; VOUT LOA x RSENSE x ROUT RGA N The current- sense amplifier’s gain accuracy is therefore the ratio match of ROUT to RGAIN. For each of the four gain options available, Table 1 lists the values for ROUT and RGAIN. The TS1100’s output stage is protected against input overdrive by use of an output current-limiting circuit of 3mA (typical) and a 7V internal clamp protection circuit. Table 1: Internal Gain Setting Resistors (Typical Values) GAIN (V/V) RGAIN (Ω) ROUT (Ω) Part Number 25 400 10k TS1100-25 50 200 10k TS1100-50 100 100 10k TS1100-100 200 100 20k TS1100-200 To achieve its very-low input offset voltage performance over temperature, VSENSE voltage, and power supply voltage, the design of the TS1100’s amplifier is chopper-stabilized, a commonly-used technique to reduce significantly the input offset voltage of amplifiers. This method, however, does employ the use of sampling techniques and therefore residue of the TS1100’s 10kHz internal clock is contained in the TS1100’s output voltage spectrum. APPLICATIONS INFORMATION Choosing the Sense Resistor Selecting the optimal value for the external RSENSE is based on the following criteria and for each commentary follows: 1) RSENSE Voltage Loss 2) VOUT Swing vs. Applied Input Voltage at VRS+ and Desired VSENSE 3) Total ILOAD Accuracy 4) Circuit Efficiency and Power Dissipation 5) RSENSE Kelvin Connections 6) Sense Resistor Composition 1) RSENSE Voltage Loss For lowest IR voltage loss in RSENSE, the smallest usable value for RSENSE should be selected. 2) VOUT Swing vs. Applied Input Voltage at VRS+ and Desired VSENSE As there is no separate power supply pin for the TS1100, the circuit draws its power from the applied voltage at both its RS+ and RS- terminals. Therefore, the signal voltage at the OUT terminal is bounded by the minimum supply voltage applied to the TS1100. Therefore, VOUT(max) = VRS+(min) - VSENSE(max) – VOH(max) and RSENSE VOUT max GA N LOA max where the full-scale VSENSE should be less than VOUT(MAX)/GA N at the application’s minimum RS+ terminal voltage. For best performance with a 3.6V power supply, RSENSE should be chosen to generate a VSENSE of: a) 120mV (for the 25V/V GAIN option), b) 60mV (for the 50V/V GAIN option), c) 30mV (for the 100V/V GAIN option), or d) 15mV (for the 200V/V GAIN option) at the full-scale ILOAD(MAX) current in each application. For the case where the minimum power supply voltage is higher than 3.6V, each of the four full-scale VSENSEs above can be increased. 3) Total ILOAD Accuracy In the TS1100 ’s linear region where VOUT < VOUT(MAX), there are two specifications related to the circuit’s accuracy: a) the TS1100’s input offset voltage (VOS = 100μV, max) and b) its gain error (GE(max) = 0.5%). |
유사한 부품 번호 - TS1100 |
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유사한 설명 - TS1100 |
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