LA72710V

No.A0237-7/10

I

(1) Data Transfer Manual

This IC adopts control method (I

clock) and SDA (serial data). At first, set up

SDA terminal with synchronized SCL terminal clock. The order of transferring is first, MSB (the Most Scale of Bit),

and save the order. The 9th bit takes ACK (Acknowledge) period, during SCL terminal takes ‘H’ this IC pull down the

SDA terminal. After transferred the necessary data, two terminals lead to set up and of

thus the transfer comes to close.

*1 Defined by SCL rise down SDA during ‘H’ period.

*2 Defined by SCL rise up SDA during ‘H’ period.

(2) Transfer Data Format

After transfer start condition, transfers slave address (1000 000*B) to SDA terminal, control data, then, stop condition

(See figure 1).

Slave address is made up of 7bits, 8th bit

IC side, this is input operation mode), and in case of ‘H’ reading mode (As this IC side, this is output operation mode).

Data works with all of bit, transfer the stop condition before stop 8bit transfer, and to stop transfer, it will be canceled

the transfer dates.

*3 It is called R/W bit.

Fig.1 DATA STRUCTURE “WRITE” mode

START Condition

Slave Address

R/WL

ACK

Control data

ACK

STOP condition

Fig.2 DATA STRUCTURE “READ” mode

START condition

Slave Address

R/WH

ACK

Internal Data *

ACK

STOP condition

∗ Output 8bits data as follows;

bit8 is result of STERO DET

(H : STEREO)

bit7 is result of BILINGUAL DET

(H : BILINGUAL)

bit6 to bit1 are fixed to ‘L’

(3) Initialize

This IC is initialized for circuit protection. Initial condition is “0 (All bits).”