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FAN9611 데이터시트(PDF) 4 Page - Fairchild Semiconductor |
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FAN9611 데이터시트(HTML) 4 Page - Fairchild Semiconductor |
4 / 36 page © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN9611 / FAN9612 • Rev. 1.1.4 4 Pin Configuration Figure 5. Pin Layout (Top-View) Pin Definitions Pin # Name Description 1 ZCD1 Zero Current Detector for Phase 1 of the interleaved boost power stage. 2 ZCD2 Zero Current Detector for Phase 2 of the interleaved boost power stage. 3 5VB 5V Bias . Bypass pin for the internal supply, which powers all control circuitry on the IC. 4 MOT Maximum On-Time adjust for the individual power stages. 5 AGND Analog Ground . Reference potential for all setup signals. 6 SS Soft-Start Capacitor . Connected to the non-inverting input of the error amplifier. 7 COMP Compensation Network connection to the output of the gM error amplifier 8 FB Feedback pin to sense the converter’s output voltage; inverting input of the error amplifier. 9 OVP Output Voltage monitor for the independent, second-level, latched OVP protection. 10 VIN Input Voltage monitor for brownout protection and input-voltage feedforward. 11 PGND Power Ground connection. 12 DRV2 Gate Drive Output for Phase 2 of the interleaved boost power stage. 13 DRV1 Gate Drive Output for Phase 1 of the interleaved boost power stage. 14 VDD External Bias Supply for the IC. 15 CS2 Current Sense Input for Phase 2 of the interleaved boost power stage. 16 CS1 Current Sense Input for Phase 1 of the interleaved boost power stage. |
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