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ADM2914-1ARQZ-RL7 데이터시트(PDF) 11 Page - Analog Devices |
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ADM2914-1ARQZ-RL7 데이터시트(HTML) 11 Page - Analog Devices |
11 / 16 page ADM2914 Rev. B | Page 11 of 16 Next, consider a −12 V input, which is specified with a ±20% input. The threshold accuracy required by the supply is chosen to be within ±5% of the −12 V rail. Therefore, the overvoltage threshold is set to −13.5 V, and the undervoltage threshold is −10.5 V. The negative voltage scheme configuration requires that the 1 V reference voltage be accounted for in Equation 1 to Equation 3. The 1 V reference voltage is subtracted from VM, VUV, and VOV, and the absolute value of the result is taken. Equation 1 becomes ( ) () () kΩ 8 . 89 10 5 1 5 . 13 1 12 ) 5 . 0 ( 6 ≈ × − − − − = − Z R Insert the value of RZ into Equation 2. ( ) () () kΩ 4 . 23 kΩ 8 . 89 10 5 1 5 . 10 1 12 ) 5 . 0 ( 6 ≈ − × − − − − = − Y R To calculate RX, insert the value of RZ and RY into Equation 3. () () ( ) MΩ 49 . 2 kΩ 4 . 23 kΩ 8 . 89 10 5 1 12 6 ≈ − − × − − = − X R POWER-UP AND POWER-DOWN On power-up, when VCC reaches 1 V, the active low UV output is asserted, and the OV output pulls up to VCC. When the vol- tage on the VCC pin reaches 1 V, the ADM2914 is guaranteed to assert UV low and OV high. When VCC exceeds 1.9 V (minimum), the VHx and VLx inputs take control. When VCC and each of the VHx inputs are valid, an internal timer begins. Subsequent to an adjustable time delay, UV weakly pulls high. UV/OV TIMING CHARACTERISTICS UV is an active low output. It is asserted when any of the four monitored voltages is below its associated threshold. When the voltage on the VCC pin is above 2 V, an internal timer holds UV low for an adjustable period, tUOTO, after the voltage on all the monitoring rails rises above their thresholds. This allows time for all monitored power supplies to stabilize after power- up. Similarly, any monitored voltage that falls below its threshold initiates a timer reset, and the timer starts again when all the monitoring rails rise above their thresholds. The UV and OV outputs are held asserted after all faults have cleared for an adjustable timeout period, determined by the value of the external capacitor attached to the TIMER pin. TIMER CAPACITOR SELECTION The UV and OV timeout period on the ADM2914 is programma- ble via the external timer capacitor, CTIMER, placed between the TIMER pin and ground. The timeout period, tUOTO, is calculated using the following equation: F/sec ) 10 )( 115 )( ( 9 − = UOTO TIMER t C Refer to Figure 15 in the Typical Performance Characteristics section, which illustrates the delay time as a function of the timer capacitor value. A minimum capacitor value of 10 pF is required. The chosen timer capacitor must have a leakage current that is less than the 1.3 μA TIMER pin charging current. To bypass the timeout period, connect the TIMER pin to VCC. tUOD tUOD tUOD tUOTO VHx UV VUOT VUOT 1V 1V VHx VHx MONITOR TIMING (TIMER PIN TIED TO VCC) VHx MONITOR TIMING UV WHEN AN INPUT IS CONFIGURED TO MONITOR A NEGATIVE VOLTAGE, VHx WILL TRIGGER AN OVERVOLTAGE CONDITION. Figure 21. VHx Positive Voltage Monitoring Timing Diagram tUOD tUOD tUOD tUOTO VLx OV VUOT VUOT 1V 1V VLx VLx MONITOR TIMING (TIMER PIN TIED TO VCC) VLx MONITOR TIMING OV WHEN AN INPUT IS CONFIGURED TO MONITOR A NEGATIVE VOLTAGE, VLx WILL TRIGGER AN UNDERVOLTAGE CONDITION. Figure 22. VLx Positive Voltage Monitoring Timing Diagram |
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