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SLA24C02-S-3 데이터시트(PDF) 11 Page - Siemens Semiconductor Group |
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SLA24C02-S-3 데이터시트(HTML) 11 Page - Siemens Semiconductor Group |
11 / 27 page SLx 24C01/02/P Semiconductor Group 11 1998-07-27 5 Write Operations Changing of the EEPROM data is initiated by the master with the command byte CSW. Depending on the state of the Write Protection pin WP and of the Protection Bits (refer to chapter 7 Page Protection Mode TM) either one byte (ByteWrite)orupto8bytes (Page Write) are modified in one programming procedure. 5.1 Byte Write Figure 7 Byte Write Sequence The erase/write cycle is finished latest after 8 ms. Acknowledge polling may be used for speed enhancement in order to indicate the end of the erase/write cycle (refer to chapter 5.3 Acknowledge Polling). Address Setting After a START condition the master transmits the Chip Select Write byte CSW. The EEPROM acknowledges the CSW byte during the ninth clock cycle. The following byte with the EEPROM address (A0 to A6 or A7) is loaded into the address counter of the EEPROM and acknowledged by the EEPROM. Transmission of Data Finally the master transmits the data byte which is also acknowledged by the EEPROM into the internal buffer. Programming Cycle Then the master applies a STOP condition which starts the internal programming procedure. The data bytes are written in thememorylocationaddressedinthe EEA byte (A0toA6or A7). The programming procedure consists of an internally timed erase/write cycle. In the first step, the selected byte is erased to “1”. With the next internal step, the addressed byte is written according to the contents of the buffer. Command Byte CSW S P C K A C K A S T A R T T P O S EEPROM Address EEA Data Byte Bus Activity Master SDA Line Bus Activity EEPROM IED02129 C K A 0 |
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