DAC714

4

SBAS032A

www.ti.com

CLK

A

0

SDI

Serial Data Input

MSB First

Latch Data

In D/A Latch

A

1

t

A0H

D

0

D

14

D

15

t

A1S

t

A1H

t

DH

t

DS

t

A0S

t

CLK

t

CH

t

CL

CLK

A

0

SDO

Serial Data

Out

t

A0S

t

A0H

D

0

D

14

Clear

D

15

t

CLK

t

CH

t

CL

CLR

t

DSOP

t

CP

t

DSOP

TIMING SPECIFICATIONS

SYMBOL

PARAMETER

MIN

MAX

UNITS

Data Clock Period

100

ns

Clock LOW

50

ns

Clock HIGH

50

ns

50

ns

50

ns

0ns

0ns

Setup Time for DATA

50

ns

Hold Time for DATA

10

ns

Output Propagation Delay

140

ns

Clear Pulsewidth

200

ns

CLK

CLR

DESCRIPTION

01

1

→ 0 → 1

1

Shift Serial Data into SDI

10

1

→ 0 → 1

1

Load D/A Latch

11

1

→ 0 → 1

1

No Change

00

1

→ 0 → 1

1

X

X

1

1

No Change

X

X

X

0

Reset D/A Latch

NOTES: X = Don’t Care. (1) All digital input changes will appear at the

output.

TRUTH TABLE

TIMING DIAGRAMS

Serial Data In

Serial Data Out