전자부품 데이터시트 검색엔진 |
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74F109SJ 데이터시트(PDF) 2 Page - Texas Instruments |
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74F109SJ 데이터시트(HTML) 2 Page - Texas Instruments |
2 / 12 page 54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description The ’F109 consists of two high-speed, completely indepen- dent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to ’F74 data sheet) by connecting the J and K inputs. Asynchronous Inputs: LOW input to S D sets Q to HIGH level LOW input to C D sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on C D and SD makes both Q and Q HIGH Features n Guaranteed 4000V minimum ESD protection. Ordering Code: See Section 0 Commercial Military Package Package Description Number 74F109PC N16E 16-Lead (0.300" Wide) Molded Dual-in-Line 54F109DM (Note 2) J16A 16-Lead Ceramic Dual-in-Line 74F109SC (Note 1) M16A 16-Lead (0.150" Wide) Molded Small Outline, JEDEC 74F109SJ (Note 1) M16D 16-Lead (0.300" Wide) Molded Small Outline, EIAJ 54F109FM (Note 2) W16A 16-Lead Cerpack 54F109LM (Note 2) E20A 16-Lead Ceramic Leadless Chip Carrier, Type C Note 1: Devices also available in 13" reel. Use suffix = SCX and SJX. Note 2: Military grade device with environmental and burn-in processing. Use suffix = DMQB, FMQB and LMQB. Logic Symbols FAST® and TRI-STATE® are registered trademarks of National Semiconductor Corporation. DS009471-3 DS009471-4 IEEE/IEC DS009471-6 November 1994 © 1997 National Semiconductor Corporation DS009471 www.national.com 1 PrintDate=1997/08/28 PrintTime=11:45:22 10182 ds009471 Rev. No. 1 cmserv Proof 1 DSXXX |
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