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CD74FCT652EN 데이터시트(PDF) 1 Page - Texas Instruments |
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CD74FCT652EN 데이터시트(HTML) 1 Page - Texas Instruments |
1 / 11 page 8-1 Data sheet acquired from Harris Semiconductor SCHS262 Features • Buffered Inputs • Typical Propagation Delay: 6.8ns at VCC = 5V, TA = 25 oC, C L = 50pF • CD75FCT651 - Inverting • CD74FCT652 - Noninverting • Family Features - SCR Latchup Resistant BiCMOS Process and Circuit Design - Speed of Bipolar FAST™/AS/S - 64mA Output Sink Current - Output Voltage Swing Limited to 3.7V at VCC = 5V - Controlled Output Edge Rates - Input/Output Isolation to VCC - BiCMOS Technology with Low Quiescent Power Description The CD74FCT651 and CD74FCT652 three-state, octal bus transceivers/registers use a small geometry BiCMOS technol- ogy. The output stage is a combination of bipolar and CMOS transistors that limits the output HIGH level to two diode drops below VCC. This resultant lowering of output swing (0V to 3.7V) reduces power bus ringing (a source of EMI) and mini- mizes VCC bounce and ground bounce and their effects dur- ing simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 64 milliamperes. These devices consist of bus transceiver circuits, D-Type flip- flops, and control circuitry arranged for multiplexed transmis- sion of data directly from the data bus or from the internal stor- age registers. Output Enables OEAB and OEBA are provided to control the transceiver functions. SAB and SBA control pins are provided to select whether real-time or stored data is transferred. The circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A LOW input level selects real-time data and a HIGH selects stored data. The following examples demonstrate the four fundamental bus management functions that can be performed with the octal bus transceivers and registers. Data on the A or B data bus, or both, can be stored in the inter- nal D flip-flops by low to high transitions at the appropriate clock pins (CAB or CBA) regardless of the select or enable control pins. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-Type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state. Pinouts Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. NO. CD74FCT651EN 0 to 70 24 Ld PDIP E24.3 CD74FCT652EN 0 to 70 24 Ld PDIP E24.3 CD74FCT651M 0 to 70 24 Ld SOIC M24.3 CD74FCT652M 0 to 70 24 Ld SOIC M24.3 NOTE: When ordering the suffix M packages, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. CD74FCT651 (PDIP, SOIC) TOP VIEW CD74FCT652 (PDIP, SOIC) TOP VIEW 1 2 3 4 5 6 7 8 9 10 11 12 CAB SAB OEAB A0 A1 A2 A3 A4 A5 A6 A7 GND 16 17 18 19 20 21 22 23 24 15 14 13 VCC SBA OEBA B0 B1 B3 B5 B6 B7 CBA B2 B4 1 2 3 4 5 6 7 8 9 10 11 12 CAB SAB OEAB A0 A1 A2 A3 A4 A5 A6 A7 GND 16 17 18 19 20 21 22 23 24 15 14 13 VCC SBA OEBA B0 B1 B3 B5 B6 B7 CBA B2 B4 January 1997 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. FAST™ is a trademark of Fairchild Semiconductor. Copyright © Harris Corporation 1997 CD74FCT651, CD74FCT652 BiCMOS FCT Interface Logic, Octal Bus Transceivers/Registers, Three-State File Number 2394.2 NOT RECOMMENDED FOR NEW DESIGNS Use CMOS Technology |
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