CDCE421ARGER datasheet(10/27 Pages) TI1

부품명	CDCE421ARGER

상세설명	Fully-Integrated, Wide Range, Low-Jitter Crystal Oscillator Clock Generator

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제조업체	TI1 [Texas Instruments]

홈페이지	http://www.ti.com

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10 / 27 page

Enter Programming Mode

0

1

t

7

t

1

t

6

t

5

t

2

t

F

t

R

t

3

t

4

CE

SDATA

DATA

SDATA

DELAYED

EEPROM Programming

CDCE421A

SCAS873 – APRIL 2009..................................................................................................................................................................................................... www.ti.com

Figure 2 shows the timing behavior of data to be written into SDATA. The sequence shown is '001100'. If the

high period is as short as t1, this period is interpreted as '0'. If the high period is as long as t3, this period is

interpreted as a '1'. This behavior is achieved by shifting the incoming signal SDATA by time t5 into signal

SDATA_DELAYED. As Figure 2 shows, SDATA_DELAYED can be used to latch (or strobe) SDATA. The

specification for the timings t1 through t7, tR and tF are shown in Table 5.

Figure 2. SDATA/CE Timing

Table 5. SDATA/CE Timing Requirements(1)

PARAMETER

MIN

TYP

MAX

UNIT

fSDATACLK

Repeat frequency of programming

60

70

80

kHz

t1

Low signal: High pulse duration

0.2 t

ms

t2

Low signal: Low pulse duration during Entering Programming sequence

0.8 t

ms

Low signal: Low pulse duration during programming bits

0.8 t

ms

t3

High signal: High pulse duration

0.8 t

ms

t4

High signal: Low pulse duration during Entering Programming sequence

0.2 t

ms

High signal: Low pulse duration during programming bits

0.2 t

ms

t6

Time-out during Entering Programming Mode and Enter Readback Mode until

16

ms

next bit must occur. High-pulse or low-pulse duration each must be less than this

time; otherwise, a time-out results.

t7

EN-high time before first SDATA can be clocked in

3 t

ms

tR/tF

Rise and fall time from 20% to 80% of VDD

2

ns

(1)

t = 1/fSDATACLK.

To program the EEPROM, follow the procedure outlined in this section.

Load all the registers in RAM by writing to Word0 ... Word5. After going back to State 2, then go to State 3

(Programming EEPROM, No Locking) or State 4 (Programming EEPROM with Locking). The contents of Word0

… to Word5 are saved in the EEPROM. Wait 10ms in State 3 or State 4 when programming the EEPROM

before moving to State 2 (idle state).

NOTE:

When writing to the device for functionality testing and verification via the serial bus,

you are only accessing the RAM. The programming of the CDCE421A can only be

performed at VCC = 3.3 V and at room temperature (+25°C).

10

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