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CDCP1803MRGETEP 데이터시트(PDF) 9 Page - Texas Instruments |
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CDCP1803MRGETEP 데이터시트(HTML) 9 Page - Texas Instruments |
9 / 24 page 130 135 140 145 150 100 300 500 700 900 1100 1300 1500 f − Frequency − MHz 3 LVPECL Outputs (P1) Running VDD = 3.3 V, TA = 255C, 50 W to VDD −2 V for LVPECL G003 PACKAGE THERMAL RESISTANCE CDCP1803-EP www.ti.com........................................................................................................................................................................................... SCAS864 – DECEMBER 2008 SUPPLY CURRENT vs FREQUENCY Figure 4. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 4-layer JEDEC test board (JESD51-7), RθJA-1 QFN-24 package thermal resistance (1) 106.6 °C/W airflow = 0 ft/min 4-layer JEDEC test board (JESD51-7) with four QFN-24 package thermal resistance RθJA-2 thermal vias of 22-mil diameter each, 55.4 °C/W with thermal vias in PCB(1) airflow = 0 ft/min (1) It is recommended to provide four thermal vias to connect the thermal pad of the package effectively with the PCB and ensure a good heat sink. Example: Calculation of the junction-lead temperature with a 4-layer JEDEC test board using four thermal vias: TChassis = 125°C (temperature of the chassis) Peffective = Imax × Vmax = 90 mA × 3.6 V = 324 mW (max power consumption inside the package) θT Junction = θJA-2 × Peffective = 55.45°C/W × 324 mW = 17.97°C TJunction = θTJunction + TChassis = 17.97°C + 125°C = 143°C (see Figure 5 for expected life with continuous 125°C operation) Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s) :CDCP1803-EP |
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