DLP Device Name

DLP Logo

Trace Code

Pin #1 ID

Ball Material

Assembly Lot Number

DLPC300ZVB

LLLLLLLL.ZZ

KOREAYYWW

G8

DLPC300

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DLPS023A – JANUARY 2012 – REVISED JULY 2012

Device Marking

The device marking consists of the fields shown in Figure 9.

Figure 9. Device Marking

SIGNAL FUNCTIONAL DESCRIPTIONS

This section describes the input/output characteristics of signals that interface to the DLPC300 by functional

groups. Table 3 includes I/O power and type characteristic references which are further described in subsequent

sections.

Table 3. Functional Pin Descriptions

TERMINAL

I/O

I/O

CLK

DESCRIPTION

POWER

TYPE

SYSTEM

NAME

NO.

DLPC300 power-on reset. Self configuration starts when a

low-to-high transition is detected on this pin. All device

power

and

clocks

must

be

stable

and

within

recommended operating conditions before this reset is de-

asserted. Note that the following 7 signals are high-

impedance while RESET is asserted:

RESET

J14

VCC18

Async

DMD_PWR_EN,

LEDDVR_ON,

LED_SEL_0,

LED_SEL_1, SPICLK, SPIDOUT, SPICS0

External pullups/-downs should be added as needed to

these signals to avoid floating inputs where these signals

are driven.

DMD park control (active-low). Is set high to enable

normal operation. PARK must be set high within 500 µs

after releasing RESET. PARK must be set low a minimum

PARK

B8

VCC_ INTF

Async

of 500 µs before any power is to be removed from the

DLPC300 or DLP3000. See System Power-Up/Down

Sequence for more details.

Reference clock crystal Input. If an external oscillator is

PLL_REFCLK_I

K15

VCC18 (filter)

N/A

used in place of a crystal, then this pin should be used as

the oscillator input.

Reference clock crystal return. If an external oscillator is

PLL_REFCLK_O

J15

VCC18 (filter)

N/A

used in place of a crystal, then this pin should be left

unconnected (floating).

(1)

Each device connected to the SPI bus must operate from VCC_FLSH.

Copyright © 2012, Texas Instruments Incorporated

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