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FPD33680 데이터시트(PDF) 5 Page - Texas Instruments |
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FPD33680 데이터시트(HTML) 5 Page - Texas Instruments |
5 / 18 page AC Electrical Characteristics Digital AC Characteristics Symbol Parameter Conditions Min Typ Max Units PW CLK Clock Period V DD1 = 3.0 to 3.6V 11.7 ns PW CLK(L) Low Clock Pulse Width 40% 60% PW CLK PW CLK(H) High Clock Pulse Width 40% 60% PW CLK t setup1 RSDS Data Setup Time 2 ns t hold1 RSDS Data Hold Time 0 ns t setup2 ENIOx Setup Time 2 ns t hold2 ENIOx Hold Time 4 ns t PLH1 Start Pulse Fall Delay C LINE =15pF 8 ns PW DIO ENIOx Pulse Width 1 2 PW CLK PW CLK1 LOAD Pulse Width 5 T CLK 5µs t LDT Last Clock to LOAD Delay 1 PW CLK t DENSU LOAD to First ENIO Setup 2 PW CLK tPOL–CLK1 POL–CLK1 Time 14 ns Analog AC Characteristics Supplies: V SS1 =VSS2 = 0.0V, VDD1 = 3.3V, VDD2 = +10.0V. Symbol Parameter Conditions Min Typ Max Units t settle 90% Output Settling Time to 90% of Final Value Figure 2 (Note 11) 6µs t 6-bit accy Output Settling Time to 6-bit accuracy (Note 11) 10 µs t RP 90% Repair Line Output Settling Time to 90% of Final Value C LOAD = 150 pF, (Note 11) 6µs t RP 6-bit accy Repair Line Output Settling Time to 6-bit accuracy C LOAD = 150 pF, (Note 11) 10 µs Note 11: VGMA1 = 9.8V, VGMA10 = 0.2V, VGMA5 = 5.2V, VGMA6 = 4.8V, [TIME0, TIME1] = [0,1]. 20071011 FIGURE 2. Test Circuit for Output Settling Time Measurements www.national.com 4 |
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