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8V18646AIPMREP 데이터시트(PDF) 2 Page - Texas Instruments

부품명 8V18646AIPMREP
상세설명  3.3-V ABT SVAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS
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SN74LVTH18646AEP, SN74LVTH182646AEP
3.3V ABT SCAN TEST DEVICES
WITH 18BIT TRANSCEIVERS AND REGISTERS
SCAS745A − DECEMBER 2003 − REVISED APRIL 2004
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
Transceiver function is controlled by output-enable (OE) and direction (DIR) inputs. When OE is low, the
transceiver is active and operates in the A-to-B direction when DIR is high or in the B-to-A direction when DIR
is low. When OE is high, both the A and B outputs are in the high-impedance state, effectively isolating
both buses.
Data flow is controlled by clock (CLKAB and CLKBA) and select (SAB and SBA) inputs. Data on the A bus is
clocked into the associated registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data
is selected for presentation to the B bus (transparent mode). When SAB is high, stored A data is selected for
presentation to the B bus (registered mode). The function of the CLKBA and SBA inputs mirrors that of CLKAB
and SAB, respectively. Figure 1 shows the four fundamental bus-management functions that can be performed
with the SN74LVTH18646A and SN74LVTH182646A.
In the test mode, the normal operation of the SCOPE bus transceivers and registers is inhibited, and the test
circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry
performs boundary-scan test operations, according to the protocol described in IEEE Std 1149.1-1990.
Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI),
test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs
other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudorandom pattern
generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The B-port outputs of SN74LVTH182646A, which are designed to source or sink up to 12 mA, include equivalent
25-
Ω series resistors to reduce overshoot and undershoot.


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