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SM32C6415DGLZ50AEP 데이터시트(PDF) 6 Page - Texas Instruments

부품명 SM32C6415DGLZ50AEP
상세설명  FIXED-POINT DIGITAL SIGNAL PROCESSORS
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1.4.3 Functional Block and CPU (DSP Core) Diagram
EMIF B
16
64
Test
C64x DSP Core
Data Path B
B Register File
B31−B16
B15−B0
Instruction Fetch
Instruction Dispatch
Advanced Instruction Packet
Instruction Decode
Data Path A
A Register File
A31−A16
A15−A0
Power-Down
Logic
.L1
.S1
.M1 .D1
.D2
.M2
.S2
.L2
SDRAM
FIFO
SBSRAM
SRAM
L1P Cache
Direct-Mapped
16K Bytes Total
Control
Registers
Control
Logic
L1D Cache
2-Way Set-Associative
16K Bytes Total
Advanced
In-Circuit
Emulation
Interrupt
Control
McBSPs:
Framing Chips:
H.100, MVIP,
SCSA, T1, E1
AC97 Devices,
SPI Devices,
Codecs
C64x Digital Signal Processor
Enhanced
DMA
Controller
(64-channel)
32
L2
Memory
1024K
Bytes
PLL
(x1, x6, x12)
Timer 2
EMIF A
McBSP1(B)
McBSP0
HPI
ZBT SRAM
Timer 1
Timer 0
McBSP2
Boot Configuration
Interrupt
Selector
16
ROM/FLASH
I/O Devices
PCI(B)
or
GPIO[8:0]
UTOPIA(B)
or
GPIO[15:9](B)
UTOPIA:
Up to 400 Mbps
Master ATMC
VCP(A)
TCP(A)
SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
www.ti.com
For more detailed information on the device compatibility and similarities/differences among the C6414,
C6415, and C6416 devices, see the How To Begin Development Today With the TMS320C6414,
TMS320C6415, and TMS320C6416 DSPs application report (literature number SPRA718).
A.
VCP and TCP decoder coprocessors are applicable to the C6416 device only.
B.
For the C6415 and C6416 devices, the UTOPIA peripheral is multiplexed with McBSP1, and the PCI peripheral is
multiplexed with the HPI peripheral and the GPIO[15:9] port. For more details on the multiplexed pins of these
peripherals, see the Device Configurations section of this data manual.
Introduction
6
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