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ADC1003S030 데이터시트(PDF) 9 Page - Integrated Device Technology |
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ADC1003S030 데이터시트(HTML) 9 Page - Integrated Device Technology |
9 / 19 page ADC1003S030_040_050_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 9 of 19 Integrated Design Technology ADC1003S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator [1] In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 0.5 ns [2] Analog input voltages producing code 0 up to and including code 1023: a) Voffset BOTTOM is the difference between the analog input which produces data equal to 00 and the reference voltage on pin RB (VRB) at Tamb = 25 C. b) Voffset TOP is the difference between reference voltage on pin RT (VRT) and the analog input which produces data outputs equal to code 1023 at Tamb = 25 C. [3] In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to pins RB and RT via offset resistors ROB and ROT as shown in Figure 3. a) The current flowing into the resistor ladder is IL VRT VRB – ROB RL ROT ++ --------------------------------------- = and the full-scale input range at the converter to cover code 0 to code 1023, is VI RL IL RL ROB RL ROT ++ --------------------------------------- VRT VRB – 0.848 VRT VRB – == = b) Since RL, ROB and ROT have similar behavior with respect to process and temperature variation, the ratio RL ROB RL ROT ++ --------------------------------------- will be kept reasonably constant from device to device. Consequently, variation of the output codes at a given input voltage depends mainly on the difference VRT VRB and its variation with temperature and supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching between each of them is optimized. [4] EG V1023 V0 – V i PP – – Vi PP – -------------------------------------------------------- 100 = [5] The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No glitches greater than 2 LSB, neither any significant attenuation are observed in the reconstructed signal. [6] The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square wave signal) in order to sample the signal and obtain correct output data. Differential phase[9] dif differential phase fclk = 40 MHz; PAL modulated ramp - 0.4 - deg Timing (fclk = 40 MHz; CL = 15 pF); see Figure 4[10] td(s) sampling delay time - 3 - ns th(o) output hold time 4 - - ns td(o) output delay time VCCO = 4.75 V - 10 13 ns VCCO = 3.15 V - 12 15 ns CL load capacitance - - 15 pF 3-state output delay times; see Figure 5 tdZH float to active HIGH delay time - 5.5 8.5 ns tdZL float to active LOW delay time - 12 15 ns tdHZ active HIGH to float delay time - 19 24 ns tdLZ active LOW to float delay time - 12 15 ns Table 6. Characteristics …continued VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V; VCCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 C to 70 C; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 15 pF and Tamb = 25C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit |
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