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SST31LF041 데이터시트(PDF) 4 Page - Silicon Storage Technology, Inc

부품명 SST31LF041
상세설명  4 Mbit Flash 1 Mbit or 256 Kbit SRAM ComboMemory
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제조업체  SST [Silicon Storage Technology, Inc]
홈페이지  http://www.sst.com/
Logo SST - Silicon Storage Technology, Inc

SST31LF041 데이터시트(HTML) 4 Page - Silicon Storage Technology, Inc

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Data Sheet
4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory
SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A
©2001 Silicon Storage Technology, Inc.
S71107-03-000
5/01
349
(or BEF#) pulse for Program operation. For Sector or Bank-
Erase, the Data# Polling is valid after the rising edge of the
sixth WE# (or BEF#) pulse. See Figure 8 for Data# Polling
timing diagram and Figure 18 for a flowchart.
Flash Toggle Bit (DQ6)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating 0s
and 1s, i.e., toggling between 0 and 1. When the internal
Program or Erase operation is completed, the toggling will
stop. The flash memory bank is then ready for the next
operation. The Toggle Bit is valid after the rising edge of the
fourth WE# (or BE#) pulse for Program operation. For Sec-
tor or Bank-Erase, the Toggle Bit is valid after the rising
edge of the sixth WE# (or BEF#) pulse. See Figure 9 for
Toggle Bit timing diagram and Figure 18 for a flowchart.
Flash Memory Data Protection
The SST31LF041/041A/043/043A flash memory bank pro-
vides both hardware and software features to protect non-
volatile data from inadvertent writes.
Flash Hardware Data Protection
Noise/Glitch Protection: A WE# or BEF# pulse of less than
5 ns will not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#
high will inhibit the Flash Write operation. This prevents
inadvertent writes during power-up or power-down.
Flash Software Data Protection (SDP)
The SST31LF041/041A/043/043A provide the JEDEC
approved Software Data Protection scheme for all flash
memory bank data alteration operations, i.e., Program and
Erase. Any Program operation requires the inclusion of a
series of three-byte sequence. The three byte-load
sequence is used to initiate the Program operation, provid-
ing optimal protection from inadvertent Write operations,
e.g., during the system power-up or power-down. Any
Erase operation requires the inclusion of six-byte load
sequence. The SST31LF041/041A/043/043A devices are
shipped with the Software Data Protection permanently
enabled. See Table 4 for the specific software command
codes. During SDP command sequence, invalid SDP com-
mands will abort the device to the Read mode, within TRC.
Concurrent Read and Write Operations
The SST31LF041/041A/043/043A provide the unique ben-
efit of being able to read from or write to SRAM, while
simultaneously erasing or programming the Flash. The
device will ignore all SDP commands when an Erase or
Program operation is in progress. This allows data alter-
ation code to be executed from SRAM, while altering the
data in Flash. The following table lists all valid states. SST
does not recommend that both bank enables, BEF# and
BES#, be simultaneously asserted.
Note that Product Identification commands use SDP;
therefore, these commands will also be ignored while an
Erase or Program operation is in progress.
Product Identification
The product identification mode identifies the devices as
either SST31LF041/043 or SST31LF041A/043A and the
manufacturer as SST. This mode may be accessed by
hardware or software operations. The hardware device ID
Read operation is typically used by a programmer to iden-
tify the correct algorithm for the SST31LF041/041A/043/
043A flash memory banks. Users may wish to use the soft-
ware product identification operation to identify the part
(i.e., using the device ID) when using multiple manufactur-
ers in the same socket. For details, see Table 3 for hard-
ware operation or Table 4 for software operation, Figure 12
for the software ID entry and read timing diagram and Fig-
ure 19 for the ID entry command sequence flowchart.
Product Identification Mode Exit/Reset
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exiting is
accomplished by issuing the Exit ID command sequence,
CONCURRENT READ/WRITE STATE TABLE
Flash
SRAM
Program/Erase
Read
Program/Erase
Write
TABLE
1: PRODUCT IDENTIFICATION
Address
Data
Manufacturer’s ID
0000H
BFH
Device ID
SST31LF041
0001H
17H
SST31LF041A
0001H
16H
SST31LF043
0001H
65H
SST31LF043A
0001H
66H
T1.2 349


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