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SST31LF021-70-4C-WH 데이터시트(PDF) 5 Page - Silicon Storage Technology, Inc |
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SST31LF021-70-4C-WH 데이터시트(HTML) 5 Page - Silicon Storage Technology, Inc |
5 / 24 page Data Sheet 2 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF021 / SST31LF021E 5 ©2001 Silicon Storage Technology, Inc. S71137-03-000 10/01 392 internal Program or Erase operation. See Table 4 for soft- ware command codes, Figure 12 for timing waveform and Figure 18 for a flowchart. Design Considerations SST recommends a high frequency 0.1 µF ceramic capac- itor to be placed as close as possible between VDD and VSS, e.g., less than 1 cm away from the VDD pin of the device. Additionally, a low frequency 4.7 µF electrolytic capacitor from VDD to VSS should be placed within 1 cm of the VDD pin. FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD TSOP (8MM X 14MM) I/O Buffers 392 ILL B1.2 Address Buffers DQ7 - DQ0 SuperFlash Memory SRAM Control Logic Address Buffers & Latches OE# BEF# WE# BES# AMS - A0 Note: AMS = Most Significant Address FUNCTIONAL BLOCK DIAGRAM A11 A9 A8 A13 A14 A17 WE# VDD BES# A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 OE# A10 BEF# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 BEF# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 392 ILL F01.3 Standard Pinout Top View Die Up A11 A9 A8 A13 A14 A17 BES# VDD WE# A16 A15 A12 A7 A6 A5 A4 SST31LF021E SST31LF021 SST31LF021 SST31LF021E |
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