전자부품 데이터시트 검색엔진 |
|
SST31LF021E-300-4C-WH 데이터시트(PDF) 4 Page - Silicon Storage Technology, Inc |
|
SST31LF021E-300-4C-WH 데이터시트(HTML) 4 Page - Silicon Storage Technology, Inc |
4 / 24 page 4 Data Sheet 2 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF021 / SST31LF021E ©2001 Silicon Storage Technology, Inc. S71137-03-000 10/01 392 after the rising edge of the sixth WE# (or BEF#) pulse. See Figure 7 for Data# Polling timing diagram and Figure 17 for a flowchart. Flash Toggle Bit (DQ6) During the internal Program or Erase operation, any con- secutive attempts to read DQ6 will produce alternating 0s and 1s, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop. The flash memory bank is then ready for the next operation. The Toggle Bit is valid after the rising edge of the fourth WE# (or BE#) pulse for Program operation. For Sec- tor or Bank-Erase, the Toggle Bit is valid after the rising edge of the sixth WE# (or BEF#) pulse. See Figure 8 for Toggle Bit timing diagram and Figure 17 for a flowchart. Flash Memory Data Protection The SST31LF021/021E flash memory bank provides both hardware and software features to protect nonvolatile data from inadvertent writes. Flash Hardware Data Protection Noise/Glitch Protection: A WE# or BEF# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when is less than 1.5V. Write Inhibit Mode: Forcing OE# low, BEF# high, or WE# high will inhibit the Flash Write operation. This prevents inadvertent writes during power-up or power-down. Flash Software Data Protection (SDP) The SST31LF021/021E provide the JEDEC approved Software Data Protection scheme for all flash memory bank data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte load sequence. The SST31LF021/021E devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid SDP commands will abort the device to the Read mode, within TRC. Concurrent Read and Write Operations The SST31LF021/021E provide the unique benefit of being able to read from or write to SRAM, while simulta- neously erasing or programming the flash. The device will ignore all SDP commands when an Erase or Program operation is in progress. This allows data alteration code to be executed from SRAM, while altering the data in flash. The following table lists all valid states. SST does not rec- ommend that both bank enables, BEF# and BES#, be simultaneously asserted. Note that Product Identification commands use SDP; therefore, these commands will also be ignored while an Erase or Program operation is in progress. Product Identification The Product Identification mode identifies the devices as either SST31LF021 or SST31LF021E and the manufac- turer as SST. This mode may be accessed by hardware or software operations. The hardware device ID Read opera- tion is typically used by a programmer to identify the correct algorithm for the SST31LF021/021E flash memory banks. Users may wish to use the software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 3 for hardware operation or Table 4 for software operation, Figure 11 for the software ID entry and read timing diagram and Figure 18 for the ID entry com- mand sequence flowchart. Product Identification Mode Exit/Reset In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exiting is accomplished by issuing the Exit ID command sequence, which returns the device to the Read operation. Please note that the software reset command is ignored during an CONCURRENT READ/WRITE STATE TABLE Flash SRAM Program/Erase Read Program/Erase Write TABLE 1: PRODUCT IDENTIFICATION Address Data Manufacturer’s ID 0000H BFH Device ID SST31LF021 0001H 18H SST31LF021E 0001H 19H T1.4 392 |
유사한 부품 번호 - SST31LF021E-300-4C-WH |
|
유사한 설명 - SST31LF021E-300-4C-WH |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |