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512 Kbit / 1 Mbit / 2 Mbit Serial Flash

SST45VF512 / SST45VF010 / SST45VF020

Advance Information

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© 2000 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice.

514-1 10/00

S71178

FEATURES:

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Single 2.7-3.6V Read and Write Operations

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Serial Interface Architecture

– SPI Compatible: Mode 0 and Mode 3

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Byte Serial Read with Single Command

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Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

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Low Power Consumption:

– Active Current: 20 mA (typical)

– Standby Current: 10 µA (typical)

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Sector or Chip-Erase Capability

– Uniform 4 KByte sectors

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Fast Erase and Byte-Program:

– Chip-Erase Time: 70 ms (typical)

– Sector-Erase Time: 18 ms (typical)

– Byte-Program Time: 14 µs (typical)

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Automatic Write Timing

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End-of-Write Detection

– Software Status

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10 MHz Max Clock Frequency

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Hardware Reset Pin (RESET#)

– Resets the device to Standby Mode

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CMOS I/O Compatibility

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Hardware Data Protection

– Protects and unprotects the device

from Write operation

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Packages Available

– 8-Pin SOIC (4.9mm x 6mm)

PRODUCT DESCRIPTION

The SST45VF512, SST45VF010 and SST45VF020 are

manufactured with SST’s proprietary, high performance

CMOS SuperFlash technology. The Serial Flash is

organized as 16 sectors of 4096 Bytes for SST45VF512,

32 sectors of 4096 Bytes for the SST45VF010 and

64 sectors of 4096 Bytes for the SST45VF020. The

memory is accessed for Read or Erase/Program by the

SPI bus compatible serial protocol. The bus signals are:

serial data input (SI), serial data output (SO), serial clock

(SCK), write protect (WP#), chip enable (CE#), and

hardware reset (RESET#).

The SST45VFxxx devices are offered in 8-pin SOIC

package. See Figure 1 for the pinout.

Device Operation

The SST45VFxxx uses bus cycles of 8 bits each for

commands, data, and addresses to execute operations.

The operation instructions are listed in Table 2.

All instructions are synchronized off a high to low transi-

tion of CE#. The first low to high transition on SCK will

initiate the instruction sequence. Inputs will be accepted

on the rising edge of SCK starting with the most signifi-

cant bit. Any low to high transition on CE# before the input

instruction completes will terminate any instruction in

progress and return the device to the standby mode.

Read

The Read operation outputs the data in order from the

initial accessed address. While SCK is input, the address

will be incremented automatically until end (top) of the

address space, then the internal address pointer auto-

matically increments to beginning (bottom) of the ad-

dress space (00000H), and data out stream will continue.

The read data stream is continuous through all ad-

dresses until terminated by a low to high transition on

CE#.

Sector/Chip-Erase Operation

The Sector-Erase operation clears all bits in the selected

sector to “FF”. The Chip-Erase instruction clears all bits

in the device to “FF”.

Byte-Program Operation

The Byte-Program operation programs the bits in the

selected byte to the desired data. The selected byte must

be in the erased state (“FF”) when initiating a Program

operation. The data is input from bit 7 to bit 0 in order.

Software Status Operation

The Status operation determines if an Erase or Program

operation is in progress. If bit 0 is at a “0” an Erase or

Program operation is in progress, the device is busy. If bit

0 is at a “1” the device is ready for any valid operation. The

status read is continuous with ongoing clock cycles until

terminated by a low to high transition on CE#.