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SST49LF020 데이터시트(PDF) 4 Page - Silicon Storage Technology, Inc

부품명 SST49LF020
상세설명  2 Megabit LPC Flash
Download  38 Pages
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제조업체  SST [Silicon Storage Technology, Inc]
홈페이지  http://www.sst.com/
Logo SST - Silicon Storage Technology, Inc

SST49LF020 데이터시트(HTML) 4 Page - Silicon Storage Technology, Inc

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Advance Information
2 Megabit LPC Flash
SST49LF020
©2001 Silicon Storage Technology, Inc.
S71175-02-000
5/01
526
PARALLEL PROGRAMMING MODE
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. The data portion of the software com-
mand sequence is latched on the rising edge of WE#.
During the software command sequence the row address
is latched on the falling edge of R/C# and the column
address is latched on the rising edge of R/C#.
Read
The Read operation of the SST49LF020 device is con-
trolled by OE#. OE# is the output control and is used to
gate data from the output pins. Refer to the Read cycle
timing diagram, Figure 15, for further details.
Reset
Driving the RST# low will initiate a hardware reset of the
SST49LF020.
Byte-Program Operation
The SST49LF020 device is programmed on a byte-by-byte
basis. The Byte-Program operation is initiated by executing
a four-byte-command load sequence for Software Data Pro-
tection with address (BA) and data in the last byte
sequence. During the Byte-Program operation, the row
address (A10-A0) is latched on the falling edge of R/C# and
the column address (A21-A11) is latched on the rising edge
of R/C#. The data bus is latched on the rising edge of WE#.
The Program operation, once initiated, will be completed,
within 20 µs. See Figures 7 and 19 for Program operation
timing diagram and Figure 31 for its flowchart. During the
Program operation, the only valid reads are Data# Polling
and Toggle Bit. During the internal Program operation, the
host is free to perform additional tasks. Any commands writ-
ten during the internal Program operation will be ignored.
Sector-Erase Operation
The Sector-Erase operation allows the system to erase
the device on a sector-by-sector basis. The sector archi-
tecture is based on uniform sector size of 4 KByte. The
Sector-Erase operation is initiated by executing a six-byte-
command load sequence for Software Data Protection
with Sector-Erase command (30H) and sector address
(SA) in the last bus cycle. The internal Erase operation
begins after the sixth WE# pulse. The End-of-Erase can
be determined using either Data# Polling or Toggle Bit
methods. See Figure 20 for Sector-Erase timing wave-
forms. Any commands written during the Sector-Erase
operation will be ignored.
Block-Erase Operation
The Block-Erase Operation allows the system to erase the
device in 16 KByte uniform block size. The Block-Erase
operation is initiated by executing a six-byte-command
load sequence for Software Data Protection with Block-
Erase command (50H) and block address. The internal
Block-Erase operation begins after the sixth WE# pulse.
The End-of-Erase can be determined using either Data#
Polling or Toggle Bit methods. See Figure 21 for Block-
Erase timing waveforms. Any commands written during
the Block-Erase operation will be ignored.
Chip-Erase
The SST49LF020 device provides a Chip-Erase operation
only in PP Mode, which allows the user to erase the entire
memory array to the “1” state. This is useful when the entire
device must be quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte Software Data Protection command sequence with
Chip-Erase command (10H) with address 5555H in the last
byte sequence. The internal Erase operation begins with
the rising edge of the sixth WE#. During the internal Erase
operation, the only valid read is Toggle Bit or Data# Polling.
See Table 4 for the command sequence, Figure 22 for
Chip-Erase timing diagram, and Figure 34 for the flowchart.
Any commands written during the Chip-Erase operation
will be ignored.
Write Operation Status Detection
The SST49LF020 device provides two software means
to detect the completion of a Write (Program or Erase)
cycle, in order to optimize the system write cycle time.
The software detection includes two status bits: Data#
Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write
detection mode is enabled after the rising edge of WE#
which initiates the internal Program or Erase operation.
The actual completion of the nonvolatile write is asyn-
chronous with the system; therefore, either a Data# Poll-
ing or Toggle Bit read may be simultaneous with the
completion of the Write cycle. If this occurs, the system
may possibly get an erroneous result, i.e., valid data may
appear to conflict with either DQ7 or DQ6. In order to pre-
vent spurious rejection, if an erroneous result occurs, the
software routine should include a loop to read the
accessed location an additional two (2) times. If both
reads are valid, then the device has completed the Write
cycle, otherwise the rejection is valid.


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