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전자부품 데이터시트 검색엔진 |
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SST31LF043-300-4E-WI 데이터시트(PDF) 3 Page - Silicon Storage Technology, Inc |
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SST31LF043-300-4E-WI 데이터시트(HTML) 3 Page - Silicon Storage Technology, Inc |
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3 / 26 page  Data Sheet 4 Mbit Flash + 1 Mbit or 256 Kbit SRAM ComboMemory SST31LF041 / SST31LF041A / SST31LF043 / SST31LF043A 3 ©2001 Silicon Storage Technology, Inc. S71107-03-000 5/01 349 output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. See Figure 5 for the Read cycle timing diagram. Flash Erase/Program Operation SDP commands are used to initiate the flash memory bank Program and Erase operations of the SST31LF041/041A/ 043/043A. SDP commands are loaded to the flash mem- ory bank using standard microprocessor write sequences. A command is loaded by asserting WE# low while keeping BEF# low and OE# high. The address is latched on the fall- ing edge of WE# or BEF#, whichever occurs last. The data is latched on the rising edge of WE# or BEF#, whichever occurs first. Flash Byte-Program Operation The flash memory bank of the SST31LF041/041A/043/ 043A devices are programmed on a byte-by-byte basis. Before the Program operations, the memory must be erased first. The Program operation consists of three steps. The first step is the three-byte-load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte-Program operation, the addresses are latched on the falling edge of either BEF# or WE#, whichever occurs last. The data is latched on the ris- ing edge of either BEF# or WE#, whichever occurs first. The third step is the internal Program operation which is ini- tiated after the rising edge of the fourth WE# or BEF#, whichever occurs first. The Program operation, once initi- ated, will be completed, within 20 µs. See Figures 6 and 7 for WE# and BEF# controlled Program operation timing diagrams and Figure 17 for flowcharts. During the Program operation, the only valid Flash Read operations are Data# Polling and Toggle Bit. During the internal Program opera- tion, the host is free to perform additional tasks. Any SDP commands loaded during the internal Program operation will be ignored. Flash Sector-Erase Operation The Sector-Erase operation allows the system to erase the flash memory bank on a sector-by-sector basis. The sector architecture is based on uniform sector size of 4 KBytes. The Sector-Erase operation is initiated by executing a six- byte-command load sequence for Software Data Protec- tion with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The address lines A18-A12 will be used to determine the sector address. The sector address is latched on the falling edge of the sixth WE# pulse, while the command (30H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods. See Fig- ure 10 for timing waveforms. Any SDP commands loaded during the Sector-Erase operation will be ignored. Flash Bank-Erase Operation The SST31LF041/041A/043/043A flash memory bank pro- vides a Bank-Erase operation, which allows the user to erase the entire flash memory bank array to the “1s” state. This is useful when the entire bank must be quickly erased. The Bank-Erase operation is initiated by executing a six- byte Software Data Protection command sequence with Bank-Erase command (10H) with address 5555H in the last byte sequence. The internal Erase operation begins with the rising edge of the sixth WE# or BEF# pulse, whichever occurs first. During the internal Erase operation, the only valid Flash Read operations are Toggle Bit and Data# Poll- ing. See Table 4 for the command sequence, Figure 11 for timing diagram, and Figure 20 for the flowchart. Any SDP commands loaded during the Bank-Erase operation will be ignored. Flash Write Operation Status Detection The SST31LF041/041A/043/043A flash memory bank pro- vides two software means to detect the completion of a flash memory bank Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual comple- tion of the nonvolatile write is asynchronous with the sys- tem; therefore, either a Data# Polling or Toggle Bit Read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an errone- ous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Flash Data# Polling (DQ7) When the SST31LF041/041A/043/043A flash memory bank is in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will pro- duce true data. The flash memory bank is then ready for the next operation. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of the fourth WE# |
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