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SST89C54-33-I-TQI 데이터시트(PDF) 6 Page - Silicon Storage Technology, Inc |
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SST89C54-33-I-TQI 데이터시트(HTML) 6 Page - Silicon Storage Technology, Inc |
6 / 50 page 6 © 2000 Silicon Storage Technology, Inc. 344-2 8/00 FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications TABLE 1: PIN DESCRIPTIONS Symbol Type1 Name and Functions P0[7:0] I/O1 Port 0: Port 0 is an 8-bit open drain bi-directional I/O port. As an output port each pin can sink several LS TTL inputs. Port 0 pins that have 1’s written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external memory. In this application it uses strong internal pull-ups when transitioning to 1’s. Port 0 also receives the code bytes during FLASH MEMORY programming, and outputs the code bytes during program verification. External pull-ups are required during program verification. P1[7:0] I/O with internal Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 pull-ups output buffers can drive LS TTL inputs. Port 1 pins that have 1’s written to them are pulled high by the internal pull-ups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current (IIL, on the data sheet) because of the internal pull-ups. P1(5, 6, 7) have high current drive of 16mA. Port 1 also receives the low-order address bytes during FLASH MEMORY programming and program verification. P1[0] I T2: (external count input to Timer/Counter 2), clock-out P1[1] I T2EX: (Timer/Counter 2 capture/reload trigger and direction control) P2[7:0] I/O with internal Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins pull-ups that have 1’s written to them are pulled high by the internal pull-ups, and in that state can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current (IIL, on the data sheet) because of the internal pull-ups. Port 2 sends the high-order address byte during fetches from external Program memory and during accesses to external Data Memory that use 16-bit address (MOVX@DPTR). In this application it uses strong internal pull-ups when outputting 1’s. During accesses to external Data Memory that use 8-bit addresses (MOVX@Ri), Port 2 sends the contents of the P2 Special Function Register. Port 2 also receives some control signals and a partial of high-order address bits during FLASH MEMORY programming and program verification. P3[7:0] I/O with internal Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 pull-ups output buffers could drive LS TTL inputs. Port 3 pins that have 1’s written to them are pulled high by the internal pull-ups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current (IIL, on the data sheet) because of the pull-ups. Port 3 also serves the functions of various special features of the FlashFlex51 Family. Port 3 also receives some control signals and a partial of high-order address bits during FLASH MEMORY programming and program verification. P3[0] I RXD: Serial input line P3[1] O TXD: Serial output line P3[2] I INT0#: External Interrupt 0 P3[3] I INT1#: External Interrupt 1 P3[4] I T0: Timer 0 external input P3[5] I T1: Timer 1 external input P3[6] O WR#: External Data Memory Write strobe P3[7] O RD#: External Data Memory Read strobe |
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