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SN74GTLPH32916ZKFR 데이터시트(PDF) 4 Page - Texas Instruments |
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SN74GTLPH32916ZKFR 데이터시트(HTML) 4 Page - Texas Instruments |
4 / 18 page www.ti.com FUNCTIONAL DESCRIPTION (CONTINUED) SN74GTLPH32916 34-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS SCES380A – JANUARY 2002 – REVISED JUNE 2005 Additionally, it allows for transparent conversion of CLKAB-to-GTLP signal levels (CLKOUT) and CLKOUT-to-LVTTL logic levels (CLKIN). Data flow in each direction is controlled by clock enables (CEAB and CEBA), latch enables (LEAB and LEBA), clock (CLKAB and CLKBA), and output enables (OEAB and OEBA). CEAB and CEBA enable all 17 bits, and OEAB and OEBA control the 17 bits of data and the CLKOUT/CLKIN buffered clock path for the A-to-B and B-to-A directions, respectively. For A-to-B data flow, when CEAB is low, the device operates on the low-to-high transition of CLKAB for the flip-flop and on the high-to-low transition of LEAB for the latch path, i.e., if CEAB and LEAB are low, the A data is latched, regardless of the state of CLKAB (high or low) and if LEAB is high, the device is in transparent mode. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. The data flow for B to A is similar to A to B, except CEBA, OEBA, LEBA, and CLKBA are used. FUNCTION TABLES xxx OUTPUT ENABLE(1) INPUTS OUTPUT B MODE CEAB OEAB LEAB CLKAB A X H X X X Z Isolation L L L H X B0(2) Latched storage of A data L L L L X B0(3) X L H X L L True transparent X L H X H H L L L ↑ L L Clocked storage of A data L L L ↑ H H H L L X X B0(3) Clock inhibit (1) A-to-B data flow is shown. B-to-A data flow is similar, but uses CEBA, OEBA, LEBA, and CLKBA. The condition when OEAB and OEBA are both low at the same time is not recommended. (2) Output level before the indicated steady-state input conditions were established, provided that CLKAB was high before LEAB went low (3) Output level before the indicated steady-state input conditions were established BUFFERED CLOCK INPUTS OPERATION OR MODE FUNCTION CE LE OEAB OEBA X X H H Z Isolation X X L H CLKAB to CLKOUT True delayed clock signal X X H L CLKOUT to CLKIN CLKAB to CLKOUT, True delayed clock signal X X L L CLKOUT to CLKIN with feedback path(1) (1) This condition is not recommended. 4 |
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