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SST89C54-33-C-TQJ 데이터시트(PDF) 10 Page - Silicon Storage Technology, Inc |
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SST89C54-33-C-TQJ 데이터시트(HTML) 10 Page - Silicon Storage Technology, Inc |
10 / 50 page 10 © 2000 Silicon Storage Technology, Inc. 344-2 8/00 FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications Memory Re-mapping The SST89C54/58 memory re-mapping feature allows users to reorganize internal Flash memory sectors so that interrupts may be serviced when Block 0 of the internal Flash is being programmed. Since Block 0 occupies the low order program address space of the 8051 architecture where the interrupt vectors reside, those interrupt vectors will normally not be available when Block 0 is being programmed. SST89C54/58 provides four options of Memory Re- mapping (Refer to Table 2). When the lowest 4 KBytes are remapped, any program access within logical ad- dress range 0000h – 0FFFh will have the 4 most signifi- cant address bits forced to “1”, redirecting the access to F000h – FFFFh. Note that the physical contents of the re-mapped portion of Block 0 (i.e. physical locations 0000h – 0FFFh in the current example) will not be accessible. Block 1 will still also be accessible through F000h – FFFFh. Figures 7 and 8 show re-mapped program memory organization for the SST89C54/58. FIGURE 6: SST89C58 PROGRAM MEMORY ORGANIZATION 344 ILL F11.1 32 KByte EXTERNAL 64 KByte EXTERNAL 32 KByte INTERNAL (Block 0) 28 KByte EXTERNAL 32 KByte INTERNAL (Block 0) 4 KByte INTERNAL (Block 1) EA# = 1 & SFCF[7] = 1 EA# = 1 & SFCF[7] = 0 EA# = 0 FFFFh EFFFh F000h 8000h 0000h 7FFFh FFFFh 8000h 0000h FFFFh 0000h 7FFFh |
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