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SN74F323N 데이터시트(PDF) 1 Page - Texas Instruments |
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SN74F323N 데이터시트(HTML) 1 Page - Texas Instruments |
1 / 8 page SN74F323 8BIT UNIVERSAL SHIFT STORAGE REGISTER WITH SYNCHRONOUS CLEAR AND 3STATE OUTPUTS SDFS072A − D2932, MARCH 1987 − REVISED OCTOBER 1993 Copyright 1993, Texas Instruments Incorporated 2−1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 • Four Modes of Operation: Hold (Store) Shift Right Shift Left Load Data • Operates With Outputs Enabled or at High Impedance • 3-State Outputs Drive Bus Lines Directly • Can Be Cascaded for N-Bit Word Lengths • Synchronous Clear • Applications: Stacked or Push-Down Registers Buffer Storage Accumulator Registers • Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs description This 8-bit universal register features multiplexed I/O ports to achieve full 8-bit data handling in a single 20-pin package. Two function-select (S0, S1) and two output-enable (OE1, OE2) inputs can be used to choose the modes of operation listed in the function table. Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputs in a high-impedance state and permits data that is applied on the I/O ports to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs synchronously when the clear (CLR) input is low. Taking either OE1 or OE2 high disables the outputs but this has no effect on clearing, shifting, or storage of data. The SN74F323 is characterized for operation from 0 °C to 70°C. FUNCTION TABLE MODE INPUTS I/O PORTS OUTPUTS MODE CLR S1 S0 OE1† OE2† CLK SL SR A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH QA′ QH′ L X L L L ↑ X X L L L L L L L L L L Clear L L XL L ↑ X XL LLLLLLL L L Clear L H HX X ↑ X XX XXXXXXX L L Hold H L L L L X X X QA0 QB0 QC0 QD0 QE0 QF0 QG0 QH0 QA0 QH0 Hold H X XL LL X XQA0 QB0 QC0 QD0 QE0 QF0 QG0 QH0 QA0 QH0 Shift H L H L L ↑ X H H QAn QBn QCn QDn QEn QFn QGn H QGn Shift Right H L HL L ↑ X LL QAn QBn QCn QDn QEn QFn QGn L QGn Shift H H L L L ↑ H X QBn QCn QDn QEn QFn QGn QHn H QBn H Shift Left H H LL L ↑ L XQBn QCn QDn QEn QFn QGn QHn LQBn L Load H H H X X ↑ X X a b c d e f g h a h NOTE: a ...h = the level of the steady-state input at inputs A through H, respectively. These data inputs are loaded into the flip-flops while the flip-flop outputs are isolated from the I/O terminals. † When one or both output-enable inputs are high the eight I/O terminals are disabled to the high-impedance state; however, sequential operation or clearing of the register is not affected. DW OR N PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 S0 OE1 OE2 G/QG E/QE C/QC A/QA QA′ CLR GND VCC S1 SL QH′ H/QH F/QF D/QD B/QB CLK SR PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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