SN74AHCT00EP

QUADRUPLE 2INPUT POSITIVENAND GATES

SCLS507 − JUNE 2003

1

POST OFFICE BOX 655303

− One Assembly/Test Site, One Fabrication

Site

−55

°C to 125°C

Sources (DMS) Support

† Component qualification in accordance with JEDEC and industry

standards to ensure reliable operation over an extended

temperature range. This includes, but is not limited to, Highly

Accelerated Stress Test (HAST) or biased 85/85, temperature

cycle, autoclave or unbiased HAST, electromigration, bond

intermetallic life, and mold compound life. Such qualification testing

should not be viewed as justifying use of this component beyond

specified performance and environmental limits.

JESD 17

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

description/ordering information

The ’AHCT00 device performs the Boolean function Y = A

• B or Y = A + B in positive logic.

ORDERING INFORMATION

TA

PACKAGE‡

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

−55

°C to 125°C

SOIC − D

Tape and reel

SN74AHCT00MDREP

AHCT00MEP

−55

°C to 125°C

TSSOP − PW

Tape and reel

SN74AHCT00MPWREP

AHT00EP

‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

A

B

OUTPUT

Y

H

H

L

L

XH

X

L

H

logic diagram, each gate (positive logic)

A

B

Y

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1A

1B

1Y

2A

2B

2Y

GND

4B

4A

4Y

3B

3A

3Y

D OR PW PACKAGE

(TOP VIEW)

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Copyright

 2003, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.