LC72722PMS

No. A2156-9/18

CCB Input data format

(1) Synchronization protection (forward protection) method setting (4bits) : FS0 to FS3

FS3 = 0 : If offset words in the correct order could not be detected continuously during the number of blocks

specified by FS0 to FS2, take that to be a lost synchronization sate.

FS3 = 1 : If blocks with uncorrectable errors were received consecutively during the number of blocks specified by

FS0 to FS2, take that to be a lost synchronization state.

F

S

0

F

S

1

F

S

2

Condition for detecting lost synchronization

0

0

0

If 3 consecutive blocks matching the FS3 condition are received.

1

0

0

If 4 consecutive blocks matching the FS3 condition are received.

0

1

0

If 5 consecutive blocks matching the FS3 condition are received.

1

1

0

If 6 consecutive blocks matching the FS3 condition are received.

0

0

1

If 8 consecutive blocks matching the FS3 condition are received.

1

0

1

If 10 consecutive blocks matching the FS3 condition are received.

0

1

1

If 12 consecutive blocks matching the FS3 condition are received.

1

1

1

If 16 consecutive blocks matching the FS3 condition are received.

Initial value : FS0 = 0, FS1 = 1, FS2 = 0, FS3 = 0

(2) Synchronization detection method setting (1bit) : BS

BS

Synchronization detection conditions

0

If during 3 blocks, 2 blocks of offset words were detected in the correct order.

1

If the offset words were detected in the correct order in 2 consecutive blocks.

Initial value : BS = 0

DI

B

0

0

B

1

1

B

2

0

B

3

1

A

0

0

A

1

1

A

2

1

A

3

0

[1] CCB address 6A

F

S

0

F

S

1

F

S

2

F

S

3

B

S

S

Y

R

O

W

E

E

C

0

E

C

1

E

C

2

E

C

3

E

C

4

C

T

0

(12) Circuit control

(5) Error correction method setting

(4) RAM write control

(3) Synchronization and RAM address reset

(2) Synchronization detection method setting

(1) Synchronization protection method setting

IN1 data, first bit

DI

B

0

1

B

1

1

B

2

0

B

3

1

A

0

0

A

1

1

A

2

1

A

3

0

[2] CCB address 6B

C

T

1

S

P

0

S

P

1

X

S

P

L

0

P

L

1

P

T

0

P

T

1

P

T

2

T

S

0

T

S

1

T

S

2

(11) Test mode settings

(10) Output pin settings

(9) RDS/RBDS selection

(8) Demodulation circuit phase control

(7) Crystal oscillator frequency selection

(12) Circuit control

IN2 data, first bit

R

M

T

S

3

Caution : The bits labeled with an asterisk must be set to 0.

(6) Intermittent DO output setting