AD1852

–8–

REV. 0

Note that the AD1852 is capable of a 32

× F

“packed mode” where the MSB is left-justified to an L/

RCLK

transition, and the LSB is right-justified to the opposite L/

RCLK

transition. L/

RCLK is HI for the left channel, and LO for the

right channel. Data is valid on the rising edge of BLCK. Packed

mode can be used when the AD1852 is programmed in right-

justified or left-justified mode. Packed mode is shown is Figure 5.

Master Clock Autodivide Feature

The AD1852 has a circuit that autodetects the relationship

between master clock and the incoming serial data, and inter-

nally sets the correct divide ratio to run the interpolator and

modulator. The allowable frequencies for each mode are shown

above. Master clock should be synchronized with L/

RCLK but

phase relation between master clock and L/

RCLK is not critical.

D15

D14

D0

CDATA

CCLK

CLATCH

Figure 7. Serial Control Port Timing

Table II.

Nominal Input

Internal Sigma-

Chip Mode

Allowable Master Clock Frequencies

Sample Rate

Delta Clock Rate

INT8

× Mode

256

× F

× F

× F

× F

× F

S

48 kHz

128

× F

S

INT4

× Mode

128

× F

× F

× F

× F

× F

S

96 kHz

64

× F

S

INT2

× Mode

64

× F

× F

× F

× F

× F

S

192 kHz

32

× F

S

SPI REGISTER DEFINITIONS

The SPI port allows flexible control of many chip parameters. It is

organized around three registers; a LEFT-CHANNEL VOLUME

register, a RIGHT-CHANNEL VOLUME register, and a

CONTROL register. Each WRITE operation to the AD1852

SPI control port requires 16 bits of serial data in MSB-first format.

The bottom two bits are used to select one of three registers,

and the top 14 bits are then written to that register. This allows

a write to one of the three registers in a single 16-bit transaction.

The SPI CCLK signal is used to clock in the data. The incom-

ing data should change on the falling edge of this signal. At the

end of the 16 CCLK periods, the CLATCH signal should rise

to clock the data internally into the AD1852.