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AD1859JRS 데이터시트(PDF) 7 Page - Analog Devices |
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AD1859JRS 데이터시트(HTML) 7 Page - Analog Devices |
7 / 16 page AD1859 REV. A –7– (continued from page 1) The AD1859 has a simple but very flexible serial data input port that allows for glueless interconnection to a variety of ADCs, DSP chips, AES/EBU receivers and sample rate converters. The serial data input port can be configured in left-justified, I 2S-justified, right-justified and DSP serial port compatible modes. The AD1859 accepts 16- or 18-bit serial audio data in MSB-first, twos-complement format. A power-down mode is offered to minimize power consumption when the device is inac- tive. The AD1859 operates from a single +5 V power supply. It is fabricated on a single monolithic integrated circuit using a 0.6 µM CMOS double polysilicon, double metal process, and is housed in 28-pin SOIC and SSOP packages for operation over the temperature range –40 °C to +105°C. THEORY OF OPERATION The AD1859 offers the advantages of sigma-delta conversion architectures (no component trims, low cost CMOS process technology, superb low level linearity performance) with the advantages of conventional multibit R-2R resistive ladder audio DACs (no requirement for any high frequency synchronous master clocks [e.g., 256 or 384 × F S] continuously variable sample rate support, jitter tolerance, low output noise, etc.). The use of a multibit sigma-delta modulator means that the AD1859 generates dramatically lower amounts of out-of-band noise energy, which greatly reduces the requirement on post DAC filtering. The required post-filtering is integrated on the AD1859. The AD1859’s multibit sigma-delta modulator is also highly immune to digital substrate noise. The digital phase locked loop feature gives the AD1859 an un- precedented jitter rejection feature. The bandwidth of the first order loop filter is 15 Hz; jitter components on the input left/right clock are attenuated by 6 dB per octave above and be- low 15 Hz. Jitter on the crystal time base or MCLK input is re- jected as well (by virtue of the on-chip switched capacitor filter), but this clock should be low jitter because it is used by the DAC to convert the audio from the discrete time (sampled) domain to the continuous time (analog) domain. The AD1859 includes an on-chip oscillator, so that the user need only provide an inexpen- sive quartz crystal or ceramic resonator as an external time base. Serial Audio Data Interface The serial audio data interface uses the bit clock (BCLK) simply to clock the data into the AD1859. The bit clock may, there- fore, be asynchronous to the L/R clock. The left/right clock (LRCLK) is both a framing signal, and the sample frequency input to the digital phase locked loop. The left/right clock (LRCLK) is the signal that the AD1859 actually uses to determine the input sample rate, and it is the jitter on LRCLK that is rejected by the digital phase locked loop. The SDATA input carries the serial stereo digital audio in MSB first, twos-complement format. Digital Interpolation Filter The purpose of the interpolator is to “oversample” the input data, i.e., to increase the sample rate so that the attenuation re- quirements on the analog reconstruction filter are relaxed. The AD1859 interpolator increases the input data sample rate by a variable factor depending on the sample frequency of the incom- ing digital audio. The interpolation is performed using a multi- stage FIR digital filter structure. The first stage is a droop equalizer; the second and third stages are half-band filters; and the fourth stage is a second-order comb filter. The FIR filter implementation is multiplier-free, i.e., the multiplies are per- formed using shift-and-add operations. Multibit Sigma-Delta Modulator The AD1859 employs a four-bit sigma-delta modulator. Whereas a traditional single bit sigma-delta modulator has two levels of quan- tization, the AD1859’s has 17 levels of quantization. Traditional single bit sigma-delta modulators sample the input signal at 64 times the input sample rate; the AD1859 samples the input sig- nal at nominally 128 times the input sample rate. The addi- tional quantization levels combined with the higher oversampling ratio means that the AD1859 DAC output spectrum contains dramatically lower levels of out-of-band noise energy, which is a major stumbling block with more traditional single bit sigma- delta architectures. This means that the post-DAC analog re- construction filter has reduced transition band steepness and attenuation requirements, which equates directly to lower phase distortion. Since the analog filtering generally establishes the noise and distortion characteristic of the DAC, the reduced requirements translate into better audio performance. Multibit sigma-delta modulators bring an additional benefit: they are essentially free of stability (and therefore potential loop oscillation) problems. They are able to use a wider range of the voltage reference, which can increase the overall dynamic range of the converter. The conventional problem which limits the performance of multibit sigma delta converters is the nonlinearity of the passive circuit elements used to sum the quantization levels. Analog Devices has developed (and been granted patents on) a revolu- tionary architecture which overcomes the component linearity problem that otherwise limits the performance of multibit sigma delta audio converters. This new architecture provides the AD1859 with the same excellent differential nonlinearity and linearity drift (over temperature and time) specifications as single bit sigma-delta DACs. The AD1859’s multibit modulator has another important ad- vantage; it has a high immunity to substrate digital noise. Sub- strate noise can be a significant problem in mixed-signal designs, where it can produce intermodulation products that fold down into the audio band. The AD1859 is approximately eight times less sensitive to digital substrate noise (voltage refer- ence noise injection) than equivalent single bit sigma-delta modulator based DACs. Dither Generator The AD1859 includes an on-chip dither generator, which is in- tended to further reduce the quantization noise introduced by the multibit DAC. The dither has a triangular Probability Dis- tribution Function (PDF) characteristic, which is generally con- sidered to create the most favorable noise shaping of the residual quantization noise. The AD1859 is among the first low cost, IC audio DACs to include dithering. Analog Filtering The AD1859 includes a second-order switched capacitor dis- crete time low-pass filter followed by a first-order analog con- tinuous time low-pass filter. These filters eliminate the need for any additional off-chip external reconstruction filtering. This on-chip switched capacitor analog filtering is essential to reduce the deleterious effects of any remaining master clock jitter. |
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