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AD1866R-REEL 데이터시트(PDF) 8 Page - Analog Devices |
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AD1866R-REEL 데이터시트(HTML) 8 Page - Analog Devices |
8 / 12 page AD1866–Digital Circuit Considerations REV. 0 –8– L S B M S B M S B L S B CLK DL DR LL LR Figure 9. AD1866 Control Signals INPUT DATA The digital input port of the AD1866 employs five signals: Data Left (DL), Data Right (DR), Latch Left (LL), Latch Right (LR), and Clock (CLK). DL and DR are the serial inputs for the left and right DACs, respectively. Input data bits are clocked into the input register on the rising edge of CLK. The falling edges of LL and LR cause the last 16 bits which were clocked into the serial registers to be shifted into the DACs, thereby up- dating the respective DAC outputs. For systems using only a single latch signal, LL and LR may be connected together. For systems using only one DATA signal, DR and DL may be con- nected together. Data is transmitted to the AD1866 in a bit stream composed of 16-bit words with a serial, twos comple- ment, MSB first format. Left and right channels share the Clock (CLK) signal. Figure 9 illustrates the general signal requirements for data transfer for the AD1866. TIMING Figure 10 illustrates the specific timing requirements that must be met in order for the data transfer to be accomplished prop- erly. The input pins of the AD1866 are both TTL and +5 V CMOS compatible. >30ns >10ns >10ns >30ns >30ns >15ns >40ns >40ns DR/DL CLK LR/LL >67ns >40ns Figure 10. AD1866 Input Signal Timing The maximum clock rate of the AD1866 is specified to be at least 13.5 MHz. This clock rate allows data transfer rates of 2 ×, 4 ×, 8×, and 16× F S (where FS equals 44.1 kHz). The applica- tions section of this data sheet contains additional guidelines for using the AD1866. |
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