ADF41020

Data Sheet

Rev. 0 | Page 8 of 16

THEORY OF OPERATION

REFERENCE INPUT SECTION

The reference input stage is shown in Figure 9. SW1 and SW2

are normally closed switches. SW3 is a normally open switch.

When power-down is initiated, SW3 is closed and SW1 and

SW2 are opened. This ensures that there is no loading of the

Figure 9. Reference Input Stage

RF INPUT STAGE

The RF input stage is shown in Figure 10. It is followed by a

buffer, which generates the differential CML levels needed for

the prescaler.

Figure 10. RF Input Stage

PRESCALER

The ADF41020 uses a two prescaler approach to achieve

operation up to 18 GHz. The first prescaler is a fixed

divide-by-4 block. The second prescaler, which takes its

input from the divide-by-4 output, is implemented as a dual-

modulus prescaler (P/P + 1), which allows finer frequency

resolution vs. a fixed prescaler. Along with the A counter and

B counter, this enables the large division ratio, N, to be realized

(N = 4(BP + A)). The dual-modulus prescaler, operating at

CML levels, takes the clock from the fixed prescaler stage and

divides it down to a manageable frequency for the CMOS A

counter and B counter. The second prescaler is programmable.

It can be set in software to 8/9, 16/17, 32/33, or 64/65. It is

based on a synchronous 4/5 core. There is a minimum divide

ratio possible for contiguous output frequencies. This minimum

A COUNTER AND B COUNTER

The A counter and B counter combine with the two prescalers

to allow a wide ranging division ratio in the PLL feedback

counter. The counters are specified to work when the prescaler

output is 350 MHz or less.

Pulse Swallow Function

Because of the fixed divide-by-4 block, the generated output

frequencies are spaced by four times the reference frequency

divided by R. The equation for VCO frequency is



R

f

A

B

P

f

IN

REF

VCO











4

)

(

where:

oscillator (VCO).

P is the preset modulus of the dual-modulus prescaler

(such as, 8/9, 16/17).

B is the preset divide ratio of the binary 13-bit counter

(2 to 8191).

A is the preset divide ratio of the binary 6-bit swallow

counter (0 to 63).

Figure 11. Prescalers, A and B Counters that Make Up the N-Divide Value

SW1

SW2

SW3

100kΩ

NC

NO

NC

BUFFER

POWER-DOWN

CONTROL

TO R COUNTER

50Ω

GND

3pF

BUFFER

TO DIVIDE BY 4

PRESCALER

LOAD

LOAD

FROM RF INPUT

BUFFER

PRESCALER

P/P + 1

13-BIT B

COUNTER

TO PFD

6-BIT A

COUNTER

N DIVIDER

MODULUS

CONTROL

N = 4(BP + A)

DIVIDE BY 4