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AD678JN 데이터시트(PDF) 9 Page - Analog Devices |
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AD678JN 데이터시트(HTML) 9 Page - Analog Devices |
9 / 14 page AD678 REV. C –9– CONVERSION CONTROL In synchronous mode (SYNC = HIGH), both Chip Select ( CS) and Start Convert ( SC) must be brought LOW to start a con- version. CS should be LOW t SC before SC is brought LOW. In asynchronous mode (SYNC = LOW), a conversion is started by bringing SC low, regardless of the state of CS. Before a conversion is started, End-of-Convert (EOC) is HIGH, and the sample-hold is in track mode. After a conversion is started, the sample-hold goes into hold mode and EOC goes LOW, signifying that a conversion is in progress. During the conversion, the sample-hold will go back into track mode and start acquiring the next sample. EOC goes HIGH when the con- version is finished. In track mode, the sample-hold will settle to ±0.01% (12 bits) in 1 µs maximum. The acquisition time does not affect the throughput rate as the AD678 goes back into track mode more than 1 µs before the next conversion. In multichannel systems, the input channel can be switched as soon as EOC goes LOW if the maximum throughput rate is needed. 12-Bit Mode Coding Format (1 LSB = 2.44 mV) Unipolar Coding Bipolar Coding (Straight Binary) (Twos Complement) VIN* Output Code VIN* Output Code 0 V 000 . . . 0 –5.000 V 100 . . . 0 5.000 V 100 . . . 0 –0.002 V 111 . . . 1 9.9976 V 111 . . . 1 +0.000 V 000 . . . 0 +2.500 V 010 . . . 0 +4.9976 V 011 . . . 1 *Code center. OUTPUT ENABLE TRUTH TABLES 12-BIT MODE (12/ 8 = HIGH) INPUTS OUTPUT ( CS U OE) DB11–DB0 1 High Z 0 Enable 12-Bit Output 8-BIT MODE (12/ 8 = LOW) INPUTS OUTPUTS R/ L HBE (CS U OE) DB11 . . . DB4 X X 1 High Z 1 0 0 0 000a b c d Unipolar 1 1 0 e f g h i j k l Mode 0 0 0 a b c d e f g h 0 1 0 i j k l 0000 1 0 0 a aaaab c d Bipolar 1 1 0 e f g h i j k 1 Mode 0 0 0 a b c d e f g h 0 1 0 i j k l 0000 NOTES 1 = HIGH voltage level. a = MSB. 0 = LOW voltage level. 1 = LSB. X = Don’t care. U = Logical OR. END-OF-CONVERT In asynchronous mode, End-of-Convert (EOC) is an open drain output (requiring a minimum 3 k Ω pull-up resistor) enabled by End-of-Convert ENable ( EOCEN). In synchronous mode, EOC is a three-state output which is enabled by EOCEN and CS. See the Conversion Status Truth Table for details. Access (tBA) and float (tFD) timing specifications do not apply in asyn- chronous mode where they are a function of the time constant formed by the 10 pF output capacitance and the pull-up resistor. START CONVERSION TRUTH TABLE INPUTS SYNC CS SC STATUS 1 1 X No Conversion Synchronous 1 0 Start Conversion Mode 1 0 Start Conversion (Not Recommended) 1 0 0 Continuous Conversion (Not Recommended) 0 X 1 No Conversion Asynchronous 0 X Start Conversion Mode 0 X 0 Continuous Conversion (Not Recommended) NOTES 1 = HIGH voltage level. 0 = LOW voltage level. X = Don’t care. X = HIGH to LOW transition. Must stay low for t = tCP. CONVERSION STATUS TRUTH TABLE INPUTS OUTPUT SYNC CS EOCEN EOC STATUS 1 0 0 0 Converting 1 0 0 1 Not Converting Synchronous 1 1 X High Z Either Mode 1 X 1 High Z Either 0 X 0 0 Converting Asynchronous 0 X 0 High Z Not Converting Mode* 0 X 1 High Z Either NOTES l = HIGH voltage level. 0 = LOW voltage level. X = Don’t care. *EOC requires a pull-up resistor in asynchronous mode. |
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