AD677

REV. A

–8–

FUNCTIONAL DESCRIPTION

The AD677 is a multipurpose 16-bit analog-to-digital converter

and includes circuitry which performs an input sample/hold

function, ground sense, and autocalibration. These functions

are segmented onto two monolithic chips—an analog signal pro-

cessor and a digital controller. Both chips are contained within

the AD677 package.

The AD677 employs a successive-approximation technique to

determine the value of the analog input voltage. However, in-

stead of the traditional laser-trimmed resistor-ladder approach,

this device uses a capacitor-array, charge redistribution tech-

nique. Binary-weighted capacitors subdivide the input sample to

perform the actual analog-to-digital conversion. The capacitor

array eliminates variation in the linearity of the device due to

temperature-induced mismatches of resistor values. Since a

capacitor array is used to perform the data conversions, the

sample/hold function is included without the need for additional

external circuitry.

Initial errors in capacitor matching are eliminated by an

autocalibration circuit within the AD677. This circuit employs

an on-chip microcontroller and a calibration DAC to measure

and compensate capacitor mismatch errors. As each error is

determined, its value is stored in on-chip memory (RAM).

Subsequent conversions use these RAM values to improve con-

version accuracy. The autocalibration routine may be invoked

at any time. Autocalibration insures high performance while

eliminating the need for any user adjustments and is described

in detail below.

The microcontroller controls all of the various functions within

the AD677. These include the actual successive approximation

algorithm, the autocalibration routine, the sample/hold opera-

tion, and the internal output data latch.

AUTO CALIBRATION

The AD677 achieves rated performance without the need for

user trims or adjustments. This is accomplished through the use

of on-chip autocalibration.

In the autocalibration sequence, sample/hold offset is nulled by

internally connecting the input circuit to the ground sense cir-

cuit. The resulting offset voltage is measured and stored in

RAM for later use. Next, the capacitor representing the most

significant bit (MSB) is charged to the reference voltage. This

charge is then transferred to a capacitor of equal size (composed

of the sum of the remaining lower weight bits). The voltage that

results represents the amount of capacitor mismatch. A calibra-

tion digital-to-analog converter (DAC) adds an appropriate

value of error correction voltage to cancel this mismatch. This

correction factor is also stored in RAM. This process is repeated

for each of the eight remaining capacitors representing the top

nine bits. The accumulated values in RAM are then used during

subsequent conversions to adjust conversion results accordingly.

As shown in Figure 1, when CAL is taken HIGH the AD677

internal circuitry is reset, the BUSY pin is driven HIGH, and

the ADC prepares for calibration. This is an asynchronous hard-

ware reset and will interrupt any conversion or calibration cur-

rently in progress. Actual calibration begins when CAL is taken

LOW and completes in 85,532 clock cycles, indicated by BUSY

going LOW. During calibration, it is preferable for SAMPLE to

be held LOW. If SAMPLE is HIGH, diagnostic data will appear

on SDATA. This data is of no value to the user.

In most applications, it is sufficient to calibrate the AD677 only

upon power-up, in which case care should be taken that the

power supplies and voltage reference have stabilized first. If

calibration is not performed, the AD677 may come up in an un-

known state, or performance could degrade to as low as 10 bits.

CONVERSION CONTROL

The AD677 is controlled by two signals: SAMPLE and CLK,

as shown in Figure 2. It is assumed that the part has been cali-

brated and the digital I/O pins have the levels shown at the start

of the timing diagram.

A conversion consists of an input acquisition followed by 17

clock pulses which execute the 16-bit internal successive ap-

proximation routine. The analog input is acquired by taking the

delay after the SAMPLE line is brought LOW, assuming the

previous conversion has completed (signified by BUSY going

LOW). Care should be taken to ensure that this negative edge is

well defined and jitter free in ac applications to reduce the un-

certainty (noise) in signal acquisition. With SAMPLE going

LOW, the AD677 commits itself to the conversion—the input

goes HIGH, and the SAMPLE input will be ignored until the

conversion is completed (when BUSY goes LOW). SAMPLE

are applied; CLK pulses that start before this period of time are

nifying that a conversion is in process, and remains HIGH until

the conversion is completed. As indicated in Figure 2, the twos

complement output data is presented MSB first. This data may

be captured with the rising edge of SCLK or the falling edge of

CLK, beginning with pulse #2. The AD677 will ignore CLK

after BUSY has gone LOW and SDATA or SCLK will not

change until a new sample is acquired.

CONTINUOUS CONVERSION

For maximum throughput rate, the AD677 can be operated in a

continuous convert mode. This is accomplished by utilizing the

fact that SAMPLE will no longer be ignored after BUSY goes

LOW, so an acquisition may be initiated even during the HIGH

time of the 17th CLK pulse for maximum throughput rate

while enabling full settling of the sample/hold circuitry. If

SAMPLE is already HIGH during the rising edge of the 17th

CLK, then an acquisition is immediately initiated approxi-

mately 100 ns after the rising edge of the 17th clock pulse.

Care must be taken to adhere to the minimum/maximum tim-

ing requirements in order to preserve conversion accuracy.

GENERAL CONVERSION GUIDELINES

During signal acquisition and conversion, care should be taken

with the logic inputs to avoid digital feedthrough noise. It is

possible to run CLK continuously, even during the sample

period. However, CLK edges during the sampling period, and

especially when SAMPLE goes LOW, may inject noise into the

sampling process. The AD677 is tested with no CLK cycles

during the sampling period. The BUSY signal can be used to

prevent the clock from running during acquisition, as illustrated