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AD7008AP20 데이터시트(PDF) 9 Page - Analog Devices |
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AD7008AP20 데이터시트(HTML) 9 Page - Analog Devices |
9 / 16 page AD7008 REV. B –9– When amplitude modulation is not required, the IQ multipliers can be bypassed (CR = 2). The sine output is directly sent to the 10-bit DAC. Digital-to-Analog Converter The AD7008 includes a high impedance current source 10-bit DAC, capable of driving a wide range of loads at different speeds. Full-scale output current can be adjusted, for optimum power and external load requirements, through the use of a single external resistor (RSET). The DAC can be configured for single or differential-ended operation. IOUT can be tied directly to AGND for single-ended operation or through a load resistor to develop an output volt- age. The load resistor can be any value required as long as the full-scale voltage developed across it does not exceed 1 volt. Since full-scale current is controlled by RSET, adjustments to RSET can balance changes made to the load resistor. DSP and MPU Interfacing The AD7008 contains a 32-bit parallel assembly register and a 32-bit serial assembly register. Each of the modulation registers can be loaded from either assembly register under control of the LOAD pin and the Transfer-Control (TC) pins (See Table II). The Command register can be loaded only from the parallel as- sembly register. In practical use, both serial and parallel inter- faces can be used simultaneously if the application requires. TC3–TC0 should be stable before the LOAD signal rises and should not change until after LOAD falls (Figure 2). The DSP/MPU asserts both WR and CS to load the parallel as- sembly register (Figure 3). At the end of each write, the parallel assembly register is shifted left by 8 or 16 bits (Depending on CR0), and the new data is loaded into the low bits. Hence, two 16-bit writes or four 8-bit writes are used to load the parallel as- sembly register. When loading parallel data, it is only necessary to write as much data as will be used by that register. For in- stance, the Command Register requires only one write to the parallel assembly register. Serial data is input to the chip on the rising edge of SCLK, most significant bit first (Figure 4). The data in the assembly regis- ters can be transferred to the modulation registers by means of the transfer control pins. Maximum Updating of the AD7008 Updating the AD7008 need not take place in a synchronous fashion. However, in asynchronous systems, most of the exter- nal clock pulses (LOAD and SCLK) must be high for greater than one system clock period. This insures that at least one CLOCK rising edge will occur successfully completing the latch function (Figure 1). However, if the AD7008 is run in a synchronous mode with the controlling DSP or microcontroller, the AD7008 may be loaded very rapidly. Optimal speed is attained when operated in the 16-bit load mode; the following discussion will assume that mode is used. Each of the modulation registers require two 16 bit loads. This data is latched into the parallel assembly register on the falling edge of the WR command. This strobe is not qualified by the CLOCK pulse but must be held low for a mini- mum of 20 ns and only need be high for 10 ns. The two 16-bit words may be loaded in succession. While the second 16-bit word is being latched into the parallel assembly register, the Transfer and Control word may be presented to the TC3–TC0 pins. If the designation register is always the same, an external register can be used to store the information on the inputs of TC3–TC0. At some time after the second falling edge of WR, the LOAD signal may go high. As long as the load signal is high 5 ns (see setup time) before the rising edge of the CLOCK sig- nal, data will be transferred to the destination register. The limiting factor of this technique is the WR period which is 30 ns. Thus the CLOCK may run up to 33 MSPS using this technique and the effective update rate would be one half or 16.5 MHz. See timing Figure 10 for timing details. DATA HI WORD WR LOW WORD CLOCK TC LOAD Figure 10. Accelerated Data Load Sequence APPLICATIONS Serial Configuration Data is written to the AD7008 in serial mode using the two sig- nal lines SDATA and SCLK. Data is accumulated in the serial assembly register with the most significant bit loaded first. The data bits are loaded on the rising edge of the serial clock. Once data is loaded in the serial assembly register, it must be trans- ferred to the appropriate register on chip. This is accomplished by setting the TC bits according to Tables II and III. If you want to load the serial assembly register into FREQ1 register, the TC bits should be 1101. When the LOAD pin is raised, data is transferred directly to the FREQ1 register. When oper- ating in serial mode, some functions must still operate in parallel mode such as loading the TC bits and updating the Command register which is accessed only through the parallel assembly register. See Figure 11 for a typical serial mode configuration. R5 390 C2 0.1µF CMD0 CMD1 CMD2 CMD3 19 20 21 22 23 24 25 26 8 9 10 11 12 13 14 15 16 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 WR TC0 TC1 TC2 TC3 WR LOAD SCLK SDATA RESET VCC VEE 50MHz U2 +5V K1115 7 14 OUT VREF COMP IOUT IOUT FSADJUST VAA VDD VDD VDD AGND DGND DGND DGND DGND TEST 44 7 18 29 43 40 3 17 28 39 +5V +5V +5V +5V 4 5 6 C1 0.1µF +5V +5V R4 49.9 2 1 R3 49.9 U3 AD7008 8 TC0 TC1 TC2 TC3 LOAD SCLK SDATA FSELECT CLK RESET SLEEP CS 27 32 33 34 35 36 41 42 31 30 38 37 Figure 11. General Purpose Serial Interface |
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