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AD73422BB-80 데이터시트(PDF) 7 Page - Analog Devices |
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AD73422BB-80 데이터시트(HTML) 7 Page - Analog Devices |
7 / 36 page REV. 0 AD73422 –7– PBGA BALL CONFIGURATION DESCRIPTIONS BGA Mnemonic Location Function VINP1 T2 Analog Input to the inverting terminal of the inverting input amplifier on Channel 1’s Positive Input. VFBP1 T1 Feedback connection from the output of the inverting amplifier on Channel 1’s positive input. When the input amplifiers are bypassed, this pin allows direct access to the positive input of Channel 1’s sigma-delta modulator. VINN1 T4 Analog Input to the inverting terminal of the inverting input amplifier on Channel 1’s Negative Input. VFBN1 T3 Feedback connection from the output of the inverting amplifier on Channel 1’s positive input. When the input amplifiers are bypassed, this pin allows direct access to the negative input of Channel 1’s sigma-delta modulator. REFOUT R7 Buffered Reference Output, which has a nominal value of 1.2 V. As the reference is common to the two codec units, the reference value is set by the wired OR of the CRC:7 bits in each codec’s status register. REFCAP R6 A Bypass Capacitor to AGND2 of 0.1 µF is required for the on-chip reference. The capacitor should be fixed to this pin. DGND P4 AFE Digital Ground/Substrate Connection. DVDD P3 AFE Digital Power Supply Connection. ARESET P5 Active Low Reset Signal. This input resets the entire chip, resetting the control registers and clearing the digital circuitry. SCLK2 P6 Output Serial Clock whose rate determines the serial transfer rate to/from the codec. It is used to clock data or control information to and from the serial port (SPORT). The frequency of SCLK is equal to the fre- quency of the master clock (AMCLK) divided by an integer number—this integer number being the prod- uct of the external master clock rate divider and the serial clock rate divider. AMCLK P7 AFE Master Clock Input. AMCLK is driven from an external clock signal. If it is required to run the DSP and AFE sections from a common clock crystal, AMCLK should be connected to the XTAL pin of the DSP section. SDO R1 Serial Data Output of the Codec. Both data and control information may be output on this pin and is clocked on the positive edge of SCLK. SDO is in three-state when no information is being transmitted and when SE is low. SDOFS R2 Framing Signal Output for SDO Serial Transfers. The frame sync is one bit wide and is active one SCLK period before the first bit (MSB) of each output word. SDOFS is referenced to the positive edge of SCLK. SDOFS is in three-state when SE is low. SDIFS R3 Framing Signal Input for SDI Serial Transfers. The frame sync is one bit wide and is valid one SCLK pe- riod before the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of SCLK and is ignored when SE is low. SDI R4 Serial Data Input of the Codec. Both data and control information may be input on this pin and are clocked on the negative edge of SCLK. SDI is ignored when SE is low. SE R5 SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the out- put pins of the SPORT are three-stated and the input pins are ignored. SCLK is also disabled internally in order to decrease power dissipation. When SE is brought high, the control and data registers of the SPORT are at their original values (before SE was brought low), however the timing counters and other internal registers are at their reset values. AGND U1 AFE Analog Ground/Substrate Connection. AVDD U2 AFE Analog Power Supply Connection. VOUTP2 U3 Analog Output from the Positive Terminal of Output Channel 2. VOUTN2 U4 Analog Output from the Negative Terminal of Output Channel 2. VOUTP1 U5 Analog Output from the Positive Terminal of Output Channel 1. VOUTN1 U6 Analog Output from the Negative Terminal of Output Channel 1. VINP2 U7 Analog Input to the inverting terminal of the inverting input amplifier on Channel 2’s Positive Input. VFBP2 T7 Feedback connection from the output of the inverting amplifier on Channel 2’s positive input. When the input amplifiers are bypassed, this pin allows direct access to the positive input of Channel 2’s sigma-delta modulator. VINN2 T6 Analog Input to the inverting terminal of the inverting input amplifier on Channel 2’s Negative Input. VFBN2 T5 Feedback connection from the output of the inverting amplifier on Channel 2’s Negative Input. When the input amplifiers are bypassed, this pin allows direct access to the negative input of Channel 2’s sigma-delta modulator. RESET H3 (Input) Processor Reset Input. BR N1 (Input) Bus Request Input. BG L1 (Output) Bus Grant Output. BGH F5 (Output) Bus Grant Hung Output. DMS A2 (Output) Data Memory Select Output. PMS B2 (Output) Program Memory Select Output. IOMS C2 (Output) Memory Select Output. BMS D3 (Output) Byte Memory Select Output. CMS D2 (Output) Combined Memory Select Output. RD C3 (Output) Memory Read Enable Output. WR B3 (Output) Memory Write Enable Output. IRQ2/ (Input) Edge- or Level-Sensitive Interrupt Request 1. PF7 D1 (Input/Output) Programmable I/O Pin. IRQL1/ (Input) Level-Sensitive Interrupt Requests 1. PF6 C1 (Input/Output) Programmable I/O Pin. |
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