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AD7467 데이터시트(PDF) 4 Page - Analog Devices |
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AD7467 데이터시트(HTML) 4 Page - Analog Devices |
4 / 15 page –4– REV. PrC Parameter B Version 1, 2 Unit Test Conditions/Comments DYNAMIC PERFORMANCE fIN =30 kHz Sine Wave, fSAMPLE=100kSPS Signal-to-Noise + Distortion (SINAD) 2 49 dB min Total Harmonic Distortion (THD) 2 –65 dB max Peak Harmonic or Spurious Noise (SFDR) 2 –65 dB max Intermodulation Distortion (IMD) 2 fa = 29.1 kHz, fb = 29.9 kHz Second Order Terms –68 dB typ Third Order Terms –68 dB typ Aperture Delay 10 ns typ Aperture Jitter 30 ps typ Full Power Bandwidth TBD MHz typ @ 3 dB Full Power Bandwidth T B D MHz typ @ 0.1 dB DC ACCURACY 2 Resolution 8 Bits Integral Nonlinearity ±0.5 LSB max Differential Nonlinearity ±0.5 LSB max Guaranteed No Missed Codes to 8 Bits Offset Error ±0.5 LSB max Gain Error ±0.5 LSB max Total Unadjusted Error (TUE) ±0.5 LSB max ANALOG INPUT Input Voltage Ranges 0 to VDD V DC Leakage Current ±1 µA max Input Capacitance 30 pF typ LOGIC INPUTS Input High Voltage, VINH 0.7(VDD) V min VDD = 1.8 to 3.6 V Input Low Voltage, VINL 0.4 V max Input Current, IIN, SCLK Pin ±1 µA max Typically 10 nA, VIN = 0 V or VDD Input Current, IIN, CS Pin ±1 µA typ Input Capacitance, CIN 2,3 10 pF max LOGIC OUTPUTS Output High Voltage, VOH VDD – 0.2 V min ISOURCE = 200 µA; VDD = 1.8 V to 3.6 V Output Low Voltage, VOL 0.2 V max ISINK = 200 µA Floating-State Leakage Current ±10 µA max Floating-State Output Capacitance 3, 4 10 pF max Output Coding Straight (Natural) Binary CONVERSION RATE Conversion Time 4.166 µs max 10 SCLK Cycles with SCLK at 2.4 MHz Track/Hold Acquisition Time TBD ns max Throughput Rate 100 kSPS max See Serial Interface Section POWER REQUIREMENTS V DD 1.8/3.6 V min/max I DD Digital I/Ps = 0 V or VDD Normal Mode (Static) 350 µA max VDD = 3V. SCLK On or Off 200 µA max VDD = 1.8 V . SCLK On or Off Power-Down Mode 0.5 µA max SCLK Off 80 µA max SCLK On Power Dissipation 5 Normal Mode (Operational) TBD mW max VDD = 3 V. fSAMPLE = TBD TBD mW max VDD = 1.8 V. fSAMPLE = TBD Power-Down 1.5 µW max VDD = 3 V. SCLK Off 0.9 µW max VDD = 1.8 V. SCLK Off NOTES 1Temperaturerangesasfollows:BVersions:–40°Cto+85°C. 2SeeTerminology. 3Sampletestedat25°Ctoensurecompliance. 4SeePowerVersusThroughputRatesection. Specificationssubjecttochangewithoutnotice. AD7468–SPECIFICATIONS1 (VDD = 1.8 V to 3.6 V, fSCLK = 2.4 MHz, fSAMPLE = 100 kSPS unless otherwise noted; TA = TMIN to TMAX, unless otherwise noted.) pecifications |
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